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SN75DP129RHHTG4 数据表(PDF) 18 Page - Texas Instruments |
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SN75DP129RHHTG4 数据表(HTML) 18 Page - Texas Instruments |
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18 / 28 page ![]() www.ti.com SDA SCL DataLine Stable; DataValid ChangeofData Allowed DataOutput byTransmitter DataOutput byReceiver SCL From Master START Condition ClockPulsefor Acknowledgement Not Acknowledge Acknowledge SCL SDA Acknowledge Acknowledge Slave Address Data SN75DP129 SLAS583A – JANUARY 2008 – REVISED MARCH 2008 Figure 24. I2C Bit Transfer Figure 25. I2C Acknowledge Figure 26. I2C Address and Data Cycles During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its address. Following this initial acknowledge by the slave, the master device becomes a receiver and acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 27 and Figure 28. See the Reading from the SN75DP129, an example section for more information. Figure 27. I2C Read Cycle 18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP129 |
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