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TMS320DM640 数据表(PDF) 30 Page - Texas Instruments |
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TMS320DM640 数据表(HTML) 30 Page - Texas Instruments |
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30 / 179 page  Memory Map Summary 30 June 2003 − Revised October 2005 SPRS222E 1.7.1 L2 Architecture Expanded Figure 1−3 shows the detail of the L2 architecture on the TMS320DM641/DM640 devices. For more information on the L2MODE bits, see the cache configuration (CCFG) register bit field descriptions in the TMS320C64x Two-Level Internal Memory Reference Guide (literature number SPRU610). 011 010 001 0x0000 0000 000 L2 Memory Block Base Address 0x0001 8000 0x0001 0000 0x0002 0000 64K-Byte RAM 32K-Byte RAM 0x0001 FFFF 32K-Byte RAM † The L2MODE = 111b is not supported on the DM641/DM640 devices. L2MODE† Figure 1−3. TMS320DM641/DM640 L2 Architecture Memory Configuration |
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