TMS320DM640 datasheet(83/179 Pages) TI

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Device Operating Conditions

June 2003 − Revised October 2005

SPRS222E

3.3

Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating

Case Temperature (Unless Otherwise Noted)

PARAMETER

TEST CONDITIONS†

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

DVDD = MIN,

IOH = MAX

2.4

VOL

Low-level output voltage

DVDD = MIN,

IOL = MAX

0.4

VI = VSS to DVDD no opposing internal

resistor

±10

Input current

VI = VSS to DVDD opposing internal

pullup resistor‡

100

150

VI = VSS to DVDD opposing internal

pulldown resistor‡

−150

−100

−50

EMIF, CLKOUT4, CLKOUT6, EMUx

−16

IOH

High-level output current

Video Ports, Timer, TDO, GPIO

(Excluding GP0[2,1]), McBSP

−8

HPI [DM641]

−0.5

EMIF, CLKOUT4, CLKOUT6, EMUx

IOL

Low-level output current

Video Ports, Timer, TDO, GPIO

(Excluding GP0[2,1]), McBSP

IOL

Low level output current

SCL0 and SDA0

HPI [DM641]

1.5

IOZ

Off-state output current

VO = DVDD or 0 V

±10

CVDD = 1.4 V, CPU clock = 600 MHz

890

ICDD

Core supply current§

CVDD = 1.2 V, CPU clock = 500 MHz

620

ICDD

Core supply current

CVDD = 1.2 V, CPU clock = 400 MHz

510

DVDD = 3.3 V, CPU clock = 600 MHz

210

IDDD

I/O supply current§

DVDD = 3.3 V, CPU clock = 500 MHz

165

IDDD

I/O supply current

DVDD = 3.3 V, CPU clock = 400 MHz

160

Input capacitance

Output capacitance

† For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.

‡ Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.

§ Measured with average activity (50% high/50% low power) at 25°C case temperature and 133-MHz EMIF for -600 speed (100-MHz EMIF for

-500 and -400 speeds). This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing

low-DSP-activity operations. The high/low-DSP-activity models are defined as follows:

High-DSP-Activity Model:

CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;

L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]

McBSP: 2 channels at E1 rate

Timers: 2 timers at maximum rate

Low-DSP-Activity Model:

CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;

L2/EMIF EDMA: None]

McBSP: 2 channels at E1 rate

Timers: 2 timers at maximum rate

The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320DMx Power Consumption

Summary application report (literature number SPRA962).

TMS320DM640 数据表(PDF) 83 Page - Texas Instruments

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