4

SP5669

ABSOLUTE MAXIMUM RATINGS

All voltages are referred to V

Characteristics

Pin

Value

Units

Conditions

Min

Max

Supply Voltage, V

CC

12

0.3

7

V

RF input voltage

13,14

2.5

V p–p

AC coupled as per application

RF input DC offset

13,14

–0.3

V

V

Port voltage

7–10

–0.3

14

V

Port in off state

7–10

–0.3

6

V

Port in on state

Total port current

7–10

50

mA

ADC input DC offset

11

–0.3

V

V

REF/COMP output DC offset

3

–0.3

V

V

Charge pump DC offset

1

–0.3

V

V

Drive DC offset

16

–0.3

V

V

Crystal oscillator DC offset

2

–0.3

V

V

Address DC offset

4

–0.3

V

V

SDA and SCL DC offset

5, 6

–0.3

6V

V

Storage temperature

–55

+150

°C

Junction temperature

+150

°C

MP16 thermal resistance

chip to ambient

111

°C/W

chip to case

41

°C/W

Power consumption at V CC =5.5V

468

mW

All ports off, prescaler enabled

ESD protection

All

4

kV

Mil Std 883 TM 3015

FUNCTIONAL DESCRIPTION

The SP5669 contains all the elements necessary, with the

exception of a frequency reference, loop filter and external high

voltage transistor, to control a varicap tuned local oscillator, so

forming a complete PLL frequency synthesised source. The

device allows for operation with a high comparison frequency

and is fabricated in high speed logic, which enables the

generation of a loop with good phase noise performance. The

block diagram is shown in Fig. 2.

The RF input signal is fed to an internal preamplifier, which

provides gain and reverse isolation from the divider signals. The

output of the preamplifier interfaces with the 17–bit fully

programmable divider via a divide–by–two prescaler. For

applications up to 2GHz RF input, the prescaler may be disabled

so eliminating the degradation in phase noise due to prescaler

action. The divider is of MN+A architecture, where the dual

modulus prescaler is 16/17, the A counter is 4–bits, and the M

counter is 13–bits.

The output of the programmable divider is fed to the phase

comparator where it is compared in both phase and frequency

domain with the comparison frequency. This frequency is

derived either from the on–board crystal controlled oscillator or

from an external reference source. In both cases the reference

frequency is divided down to the comparison frequency by the

reference divider which is programmable into 1 of 15 ratios as

detailed in Fig. 3.

The output of the phase detector feeds a charge pump and

loop amplifier section, which when used with an external high

voltage transistor and loop filter, integrates the current

pulses into the varactor line voltage. By invoking the device

test modes as described in Fig. 5, the varactor drive output

can be disabled so switching the external transistor ’off’ and

allowing an external voltage to be written to the varactor line

for tuner alignment purposes. Similarly, the charge pump

may be also disabled to a high impedance state.

The programmable divider output Fpd/2 can be

switched to port P0 by programming the device into test

mode. The test modes are described in Fig. 5

PROGRAMMING

Clock are fed in on the SDA and SCL lines respectively as

accept data (write mode) or send data (read mode). The

LSB of the address byte (R/W) sets the device into write

mode if it is low, and read mode if it is high. Tables 1 and 2

in Fig. 4 illustrate the format of the data. The device can be

programmed to respond to several addresses, which ena-

system. Table 3 in Fig.4 shows how the address is selected

by applying a voltage to the ’address’ input. When the

device receives a valid address byte, it pulls the SDA line

low during the acknowledge period, and during following

acknowledge periods after further data bytes are received.

When the device is programmed into read mode, the

controller accepting the data must pull the SDA line low

during all status byte acknowledge periods to read another

status