5

SP5669

byte. If the controller fails to pull the SDA line low during this

period, the device generates an internal STOP condition,

which inhibits further reading.

WRITE MODE

With reference to Table 1, bytes 2 and 3 contain frequency

information bits 2 14 –2 0 inclusive. Auxillary frequency bits

2 16 –2 15 are in byte 4. For most frequencies only bytes 2 and

3 will be required. The remainder of byte 4 and byte 5 control

the prescaler enable, reference divider ratio (see Fig. 3),

charge pump, REF/COMP output (see Fig. 5), output ports

and test modes (see Fig. 5).

After reception and acknowledgement of a correct address

(byte 1), the first bit of the following byte determines whether

the byte is interpreted as a byte 2 or 4, a logic ’0’ indicating byte

2 and a logic ’1’ indicating byte 4. Having interpreted this byte

as either byte 2 or 4 the following data byte will be interpreted

as byte 3 or 5 respectively. Having received two complete data

bytes, additional data bytes can be entered, where byte

interpretation follows the same procedure, without

readdressing the device. This procedure continues until a

STOP condition is received. The STOP condition can be

generated after any data byte, if however it occurs during a

byte transmission, the previous data is retained.

To facilitate smooth fine tuning, the frequency data bytes

are only accepted by the device after all 17 bits of frequency

data have been received, or after the generation of a STOP

condition. Repeatedly sending bytes 2 and 3 only will not

change the frequency. A frequency change occurs when one

of the following data sequences is sent to an addressed

device;

Bit 2 (FL) indicates whether the device is phase locked, a

logic ’1’ is present if the device is locked, and a logic ’0’ if the

device is unlocked.

Bits 6,7 and 8 (A2, A1, A0) combine to give the output of the

ADC. The ADC can be used to feed AFC information to the

ADDITIONAL PROGRAMMABLE FEATURES

Prescaler enable

The divide by two prescaler is enabled by setting bit PE within

byte 4 to a logic ’1’. A logic ’0’ disables the prescaler, directly

passing the RF input frequency to the 17–bit programmable

counter. Bit PE is a static select only.

Charge pump current

The charge pump current can be programmed by bits C1 and

C0 within data byte 5, as defined in Fig. 6.

Test mode

The test modes are invoked by setting bits RE=0 and RTS=1

within the programming data, and are selected by bits TS2,

TS1 and TS0 as shown in Fig. 5. When TS2, TS1 and TS0 are

received, the device retains previously received P2, P1 and

P0 data.

Reference/Comparison frequency output

The reference frequency F ref can be switched to the REF/

COMP output, pin 3, by setting bit RE=1 and RTS=0 within

byte 5. The comparison frequency F comp can be switched to

the REF/COMP output, pin 3, by setting bit RE=1 and RTS=1

within byte 5. For RE set to logic ’0’, the output is disabled and

set to a high state. RE and RTS default to logic ’1’ during

device power up, thus enabling the comparison frequency F

comp

at the REF/COMP output.

Bytes 2, 3, 4, 5

Bytes 4, 5, 2, 3

or when a STOP condition follows valid data bytes as

follows;

Bytes 2, 3, 4, STOP

Bytes 4, 5, 2 STOP

Bytes 2, 3, STOP

Bytes 2, STOP

Bytes 4, STOP

It should be noted that the device must be initially addressed

with both frequency AND control byte data, since the control

byte contains reference divider information which must be

provided before a chosen frequency can be synthesised. This

implies that after initial turn on, bytes 2, 3, 4 must be sent

followed by a STOP condition as a minimum requirement.

Alternatively bytes 2, 3, 4, 5 must be sent if port information is

also required.

READ MODE

When the device is in read mode, the status byte read from

the device takes the form shown in Table 2, Fig. 4.

Bit 1 (POR) is the power–on reset indicator, and this is set

to a logic ’1’ if the V

3V (at 25

°C), e.g. when the device is initially turned ON. The

POR is reset to ’0’ when the read sequence is terminated by

a STOP command. When POR is set high (at low V

programmed information is lost and the output ports are all set

to high impedance.

Comparison

frequency with a

R3

R2

R1

R0

Ratio

4MHz external

reference

0

0

0

0

2

2MHz

0

0

0

1

4

1MHz

0

0

1

0

8

500kHz

0

0

1

1

16

250kHz

0

1

0

0

32

125kHz

0

1

0

1

64

62.5kHz

0

1

0

0

128

31.25kHz

0111

256

15.625kHz

1

0

0

0

Not

-

Allowed

1

0

0

1

6

666.67kHz

1

0

1

0

12

333.33kHz

1011

24

166.67kHz

1

1

0

0

48

83.33kHz

1

1

0

1

96

41.67kHz

1

1

1

0

192

20.83kHz

1

1

1

1

384

10.42kHz

Fig. 3 Reference division ratios