SAP51D-A-G1-R datasheet(42/67 Pages) RENESAS

42 / 67 page

SAP51 / SAP5S Datasheet

January 28, 2016

Table 5.18 SAP5 Initialization Times

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNIT

Initialization time after Software Reset (generated by master

calls Reset_Slave or Broadcast_Reset) or external reset via

DSTBn

tINIT

Initialization time after power on

tINIT2

CUOUT

≤ 10µF

Initialization time after power-on with high capacitive load

tINIT3

CUOUT = 470µF

1000

Guaranteed by design.

Power starts when VLTGP = 18V at the latest.

5.13.1. Power-On Reset

In order to force the SAP5 into a defined state after power-on and to avoid uncontrolled switching of the digital

logic if the 5V supply (U5R) falls below a specified minimum level, a Power-On Reset is executed under the

conditions given in Table 5.19.

Table 5.19 Power-On Reset (POR) Threshold Voltages

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNIT

VU5R voltage to trigger internal reset procedure, falling voltage

VPOR1F

1.2

1.7

VU5R voltage to trigger initialization procedure, rising voltage

VPOR1R

3.5

4.3

Power-On Reset pulse width

tLOW

µs

Guaranteed by design.

Figure 5.5

Power-On Behavior (all modes)

LTGP

U5R

Reset

approx. 15V

tLOW

VPOR1R

VPOR1F

Note:

The Power-On Reset circuit has a threshold voltage reference. This reference matches the process

tolerance of the logic levels and therefore is not accurate. All values depend slightly on the rise and fall time of the

supply voltage.

SAP51D-A-G1-R 数据表(PDF) 42 Page - Renesas Technology Corp

SAP51D-A-G1-R 数据表(HTML) 42 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载