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SAP51D-A-G1-R 数据表(PDF) 53 Page - Renesas Technology Corp |
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SAP51D-A-G1-R 数据表(HTML) 53 Page - Renesas Technology Corp |
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53 / 67 page ![]() SAP51 / SAP5S Datasheet © 2016 Integrated Device Technology, Inc. 53 January 28, 2016 If the Loopback Mode is not active, the AS-i receiver is disabled while the SAP5 is transmitting an AS-i signal. Otherwise, the transmitted signal is read back in parallel and provided at the RX_DAT output for checkup purposes. The loopback time tLOOPBACK is mainly defined by the analog signal processing within the Receiver and the Transmitter. However, an additional delay of up to 1875ns can be inserted if necessary. Therefore, the ID_Code_Extension_2 EEPROM register must be programmed as described below. NOTE: The ID_Code_Extension_2 must be programmed before programming of the Master_Mode flag. Once the Master_Mode flag is set to logic high, the slave functionality of the SAP5 is no longer available, preventing any write access to the EEPROM by use of AS-i master requests as described in section 4.3. Table 5.27 Programmable Variation of the Loopback Time ID_Code_Extension_2 (ID2_Bit3 to ID2_Bit0) ∆t loopback 0000 0 0001 +125ns 0010 +250ns 0011 +375ns 0100 +500ns 0101 +625ns 0110 +750ns 0111 +875ns 1000 +1000ns 1001 +1125ns 1010 +1250ns 1011 +1375ns 1100 +1500ns 1101 +1625ns 1110 +1750ns 1111 +1875ns |
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