M28010 datasheet(8/23 Pages) STMICROELECTRONICS

8 / 23 page

M28010

8/23

Software Chip Erase

The device can be erased (with all bytes set to

FFh) by using a six-byte software command code.

This operation can be initiated only if the user

loads, with a Page Write addressing mode, six

specific data bytes to six specific locations (as

shown in Figure 6). The complexity of the

sequence has been designed to guard against

inadvertent use of the command.

Status Bits

The devices provide five status bits (DQ7, DQ6,

DQ5, DQ1 and DQ0) for use during write

operations. These allow the application to use the

write time latency of the device for getting on with

other work. These signals are available on the I/O

port bits DQ7, DQ6, DQ5, DQ1 and DQ0 (but only

during the internal write cycle, tQ5HQ5X).

Data Polling bit (DQ7). The internally timed write

cycle starts as soon as tWLQ5H (defined in Table

9A to Table 9C) has elapsed since the previous

byte was latched in to the memory. The value of

the DQ7 bit of this last byte, is used as a signal

throughout this write operation: it is inverted while

the internal write operation is underway, and is

inverted back to its original value once the

operation is complete.

Toggle bit (DQ6). The device offers another way

for determining when the internal write cycle is

running. During the internal write cycle, DQ6

toggles from ’0’ to ’1’ and ’1’ to ’0’ (the first read

value being ’0’) on subsequent attempts to read

any byte of the memory. When the internal write

cycle is complete, the toggling is stopped, and the

values read on DQ7-DQ0 are those of the

addressed memory byte. This indicates that the

device is again available for new Read and Write

operations.

Page Load Timer Status bit (DQ5). An internal

timer is used to measure the period between

successive

Write operations,

tWLQ5H

(defined in Table 9A to Table 9C). The DQ5 line is

held low to show when this timer is running (hence

showing that the device has received one write

operation, and is waiting for the next). The DQ5

line is held high when the counter has overflowed

(hence showing that the device is now starting the

internal write to the memory array).

Page Write Abort bit (DQ1). During a page write

operation, the A16 to A7 signals should be kept

constant.

They

should

not

change

while

successive data bytes are being transferred to the

internal latches of the memory device. If a change

occurs on any of the pins, A16 to A7, during the

page write operation (that is, before the falling

edge of W or E, which ever occurs later), the

internal write cycle is not started, and the internal

circuitry is completely reset.

The abort signal can be observed on the DQ1 pin,

using a normal read operation. This can be

performed at any time during the byte load cycle,

tWLQ5H, or while the W input is being held high

between two load cycles. The default value of DQ1

is initially set to ’0’ and changes to ’1’ if the internal

circuitry has detected a change on any of the

address pins A16 to A7. This PWA bit can be

checked regardless of whether Software Data

Protection is enabled or disabled.

Table 5A. Read Mode DC Characteristics for M28010 (5V range)

(TA = –40 to 85 °C; VCC = 4.5 to 5.5 V)

Note: 1. All inputs and outputs open circuit.

Symbol

Parameter

Test Condition

Min.

Max.

Unit

ILI

Input Leakage Current

≤ VIN ≤ VCC

µA

ILO

Output Leakage Current

0 V

≤ VOUT ≤ VCC

µA

ICC 1

Supply Current (CMOS inputs)

E= VIL,G = VIL, f = 0.1 MHz

2mA

E= VIL,G = VIL, f = 5 MHz

E=VIL,G= VIL, f = 10 MHz

ICC1

Supply Current (Stand-by) CMOS

E > VCC –0.3 V

µA

VIL

Input Low Voltage

–0.3

0.8

VIH

Input High Voltage

VCC + 0.3

VOL

Output Low Voltage

IOL = 2.1 mA

0.4

VOH

Output High Voltage

IOH = –400 µA

2.4

M28010 数据表(PDF) 8 Page - STMicroelectronics

M28010 数据表(HTML) 8 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

数据表下载