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M28010

Figure 4. Software Data Protection Enable Algorithms (with or without Memory Write)

Wait for write completion (tQ5HQ5X)

Wait for write completion (tQ5HQ5X)

Wait for write completion (tQ5HQ5X)

AI02227B

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write A0h in

Address 5555h

SDP is set

Page Write

Timing

SDP is Disabled and Application

needs to Enable it, and Write Data

Time Out (tWLQ5H)

DATA has been written

and SDP is Enabled

SDP is Disabled and

Application needs to Enable it

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write A0h in

Address 5555h

Page Write

Timing

DATA has been written

and SDP is Enabled

Time Out (tWLQ5H)

Write data

in any addresses

within one page

Write

is enabled

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write A0h in

Address 5555h

Page Write

Timing

Time Out (tWLQ5H)

Write data

in any addresses

within one page

Write

is enabled

Read

The device is accessed like a static RAM. When E

and G are low, and W is high, the contents of the

addressed location are presented on the I/O pins.

Otherwise, when either G or E is high, the I/O pins

revert to their high impedance state.

Write

Write operations are initiated when both W and E

are low and G is high. The device supports both

W-controlled and E-controlled write cycles (as

shown in Figure 12 and Figure 13). The address is

latched during the falling edge of W or E (which

ever occurs later) and the data is latched on the

rising edge of W or E (which ever occurs first).

the value specified in Table 9A to Table 9C, the

internal write cycle starts. It continues, under

internal timing control, until the write operation is

complete. The commencement of this period can

be detected by reading the Page Load Timer

Status on DQ5. The end of the internal write cycle