M28010

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Figure 5. Software Data Protection Disable Algorithms (with or without Memory Write)

Wait for write completion (tQ5HQ5X)

Wait for write completion (tQ5HQ5X)

AI02226B

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write 80h in

Address 5555h

SDP is Disabled

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write 20h in

Address 5555h

Page Write

Timing

SDP is Enabled and

Application needs to Disable it

Time Out (tWLQ5H)

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write 80h in

Address 5555h

DATA has been written

and SDP is Disabled

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write 20h in

Address 5555h

Page Write

Timing

SDP is Enabled and

Application needs to Write Data

Time Out (tWLQ5H)

Write data

in any addresses

within one page

Physical

Write

Instructions

can be detected by reading the status of the Data

Polling and the Toggle Bit functions on DQ7 and

DQ6.

Page Write

The Page Write mode allows up to 128 bytes to be

written on a single page in a single go. This is

achieved through a series of successive Write

operations, no two of which are separated by more

Table 9C).

The page write can be initiated during any byte

write operation. Following the first Byte Write

instruction, the host may send another address

and data with a minimum data transfer rate of:

The internal write cycle can start at any instant

internally timed, and continues, uninterrupted,

until completion.

All bytes must be located on the same page

address (A16-A7 must be the same for all bytes).

Otherwise, the Page Write operation is not

executed. The Page Write Abort event is indicated

to the application via DQ1 (as described on page

8).

As with the single byte Write operation, described

above, the DQ5, DQ6 and DQ7 lines can be used

to detect the beginning and end of the internally

controlled phase of the Page Write cycle.

Software Data Protection (SDP)

The device offers a software-controlled write-

protection mechanism that allows the user to

inhibit all write operations to the device, including

chip erase. This can be useful for protecting the