M28C17

16K (2K x 8) PARALLEL EEPROM

with SOFTWARE DATA PROTECTION

NOT FOR NEW DESIGN

November 1997

1/17

This is information on a product still in production but not recommended for new design.

AI01487

11

A0-A10

W

DQ0-DQ7

VCC

M28C17

G

E

VSS

8

RB

Figure 1. Logic Diagram

A0 - A10

Address Input

DQ0 - DQ7

Data Input / Output

W

Write Enable

E

Chip Enable

G

Output Enable

RB

Ready / Busy

Supply Voltage

Ground

Table 1. Signal Names

FAST ACCESS TIME: 90ns

SINGLE 5V

± 10% SUPPLY VOLTAGE

LOW POWER CONSUMPTION

FAST WRITE CYCLE:

– 64 Bytes Page Write Operation

– Byte or Page Write Cycle: 3ms Max

ENHANCED END OF WRITE DETECTION:

– Ready/Busy Open Drain Output

– Data Polling

– Toggle Bit

PAGE LOAD TIMER STATUS BIT

HIGH RELIABILITY SINGLE POLYSILICON,

CMOS TECHNOLOGY:

– Endurance >100,000 Erase/Write Cycles

– Data Retention >40 Years

JEDEC APPROVED BYTEWIDE PIN OUT

SOFTWARE DATA PROTECTION

M28C17 is replaced by the products

described on the document M28C16A

DESCRIPTION

The M28C17 is a 2K x 8 low power Parallel

EEPROM fabricated with SGS-THOMSON pro-

prietary single polysilicon CMOS technology. The

device offers fast access time with low power dis-

sipation and requires a 5V power supply.

The M28C17 offers the same features than the

M28C16, in addition to the Ready/Busy pin.

The circuit has been designed to offer a flexible

microcontroller interface featuring both hardware

28

1

PDIP28 (P)

PLCC32 (K)

28

1

SO28 (MS)

300 mils