M28C64C

M28C64X

64 Kbit (8Kb x8) Parallel EEPROM

February 1999

1/15

AI00746B

13

A0-A12

W

DQ0-DQ7

VCC

M28C64C

G

E

VSS

8

RB

Figure 1. Logic Diagram

28

1

PDIP28 (P)

PLCC32 (K)

A0 - A12

Address Input

DQ0 - DQ7

Data Input / Output

W

Write Enable

E

Chip Enable

G

Output Enable

RB

Ready / Busy

Supply Voltage

Ground

Table 1. Signal Names

FAST ACCESS TIME: 150ns

SINGLE 5V

± 10% SUPPLY VOLTAGE

LOW POWER CONSUMPTION

FAST WRITE CYCLE

– 32 Bytes Page Write Operation

– Byte or Page Write Cycle: 5ms

ENHANCED END OF WRITE DETECTION

– Ready/Busy Open Drain Output

(for M28C64C product only)

– Data Polling

– Toggle Bit

PAGE LOAD TIMER STATUS BIT

HIGH RELIABILITY SINGLE POLYSILICON,

CMOS TECHNOLOGY

– Endurance >100,000 Erase/Write Cycles

– Data Retention >40 Years

JEDEC APPROVED BYTEWIDE PIN OUT

DESCRIPTION

The M28C64C is an 8 Kbit x8 low power Parallel

EEPROM fabricated with STMicroelectronics pro-

prietary single polysilicon CMOS technology. The

device offers fast access time with low power dis-

sipation and requires a 5V power supply.

The circuit has been designed to offer a flexible

microcontroller interface featuring both hardware

and software handshakingmode with Ready/Busy,

Data Polling and Toggle Bit. The M28C64C sup-

ports 32 byte page write operation.

TSOP28 (N)

8 x13.4mm

28

1

SO28 (MS)

300 mils