A1

A0

DQ0

A7

A4

A3

A2

A6

A5

DU

A10

A8

A9

DQ7

W

A11

G

E

DQ5

DQ1

DQ2

DQ3

VSS

DQ4

DQ6

A12

RB

VCC

AI00747C

M28C64C

8

1

2

3

4

5

6

7

9

10

11

12

13

14

16

15

28

27

26

25

24

23

22

21

20

19

18

17

Figure 2A. DIP Pin Connections

Warning: DU = Don’t Use.

AI00748D

A8

A10

17

A0

NC

DQ0

A6

A3

A2

A1

A5

A4

9

A9

1

A11

DQ6

DQ7

32

M28C64C

NC

G

E

25

Figure 2B. LCC Pin Connections

Warning: NC = Not Connected, DU = Don’t Use.

A1

A0

DQ0

A5

A2

A4

A3

A9

A11

DQ7

A8

G

E

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

DU

W

A12

A6

RB

VCC

A7

AI01016D

M28C64C

28

1

22

78

14

15

21

VSS

A10

Figure 2D. TSOP Pin Connections

Warning: DU = Don’t Use.

DQ0

DQ1

A3

A0

A2

A1

A10

E

DU

DQ7

G

DQ5

VCC

DQ4

A9

W

A4

RB

A7

AI00876C

M28C64C

8

2

3

4

5

6

7

9

10

11

12

13

14

22

21

20

19

18

17

16

15

DQ2

VSS

A6

A5

DQ6

28

27

26

25

24

23

A11

DQ3

1

A12

A8

Figure 2C. SO Pin Connections

Warning: DU = Don’t Use.

PIN DESCRITPION

Addresses (A0-A12). The address inputs select

an 8-bit memory location during a read or write

operation.

Chip Enable (E). The chip enable input must be

low to enable all read/write operations. When Chip

Enable is high, power consumption is reduced.

Output Enable (G). The Output Enable input con-

trols the data output buffers and is used to initiate

read operations.

2/15

M28C64C, M28C64X