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5.7.2.

Power consumption in run mode

Table 26 Power Consumption in Run Mode when the Program is Executed in Flash

Parameter

Conditions

fHCLK

Typical value (1)

Maximum value (1)

TA=25

℃，VDD=3.3V

TA=105

℃，VDD=3.6V

IDDA

(μA)

IDD(mA）

IDDA

(μA)

IDD(mA)

Power

consumption

in run mode

HSECLK bypass (2) , enabling all

peripherals

96MHz

218.17

20.90

257.25

22.75

72MHz

152.43

15.01

183.55

16.77

48MHz

121.33

12.42

148.55

14.07

36MHz

98.50

9.43

120.42

11.23

24MHz

121.30

6.93

144.77

8.34

16MHz

91.31

4.83

111.79

6.37

8MHz

17.84

2.78

27.24

4.31

HSECLK bypass (2) , turning off all

peripherals

96MHz

217.99

11.61

253.19

12.85

72MHz

152.30

8.93

179.31

10.31

48MHz

121.29

7.70

144.81

9.00

36MHz

98.48

5.94

119.48

7.32

24MHz

121.24

4.53

144.81

5.85

16MHz

91.24

3.26

111.79

4.56

8MHz

17.84

1.98

26.08

3.30

HSICLK (2) , enabling all

peripherals

64MHz

237.41

15.13

274.23

16.00

48MHz

206.64

11.06

241.56

12.85

36MHz

184.46

8.96

218.40

10.49

24MHz

163.22

6.47

197.36

7.99

16MHz

177.22

4.53

210.87

6.22

8MHz

102.67

2.43

131.44

3.98

HSICLK (2) , turning off all

peripherals

64MHz

237.26

8.30

272.66

9.93

48MHz

206.69

6.48

240.48

8.09

36MHz

184.47

5.51

217.58

6.78

24MHz

163.15

4.10

196.21

5.33

16MHz

177.19

2.91

210.01

4.56

8MHz

102.67

1.61

131.14

3.46

Note: (1) It is obtained from a comprehensive evaluation and is not tested in production.

(2) The external clock is 8MHz, and when fHCLK>8MHz, turn on PLL, otherwise, turn off PLL.

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