M28W640ECT datasheet(5/55 Pages) STMICROELECTRONICS

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M28W640ECT, M28W640ECB

SUMMARY DESCRIPTION

The M28W640EC is a 64 Mbit (4 Mbit x 16) non-

volatile Flash memory that can be erased electri-

cally at block level and programmed in-system on

a Word-by-Word basis using a 2.7V to 3.6V VDD

supply for the circuitry and a 1.65V to 3.6V VDDQ

supply for the Input/Output pins. An optional 12V

VPP power supply is provided to speed up custom-

er programming.

The device features an asymmetrical blocked ar-

chitecture. The M28W640EC has an array of 135

blocks: 8 Parameter Blocks of 4 KWord and 127

Main Blocks of 32 KWord. M28W640ECT has the

Parameter Blocks at the top of the memory ad-

dress space while the M28W640ECB locates the

Parameter Blocks starting from the bottom. The

memory maps are shown in Figure 5, Block Ad-

dresses.

The M28W640EC features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have

three levels of protection. They can be locked and

locked-down individually preventing any acciden-

tal programming or erasure. There is an additional

hardware protection against program and erase.

When VPP ≤ VPPLK all blocks are protected against

program or erase. All blocks are locked at Power

Up.

Each block can be erased separately. Erase can

be suspended in order to perform either read or

program in any other block and then resumed.

Program can be suspended to read data in any

other block and then resumed. Each block can be

programmed and erased over 100,000 cycles.

The device includes a 192 bit Protection Register

to increase the protection of a system design. The

Protection Register is divided into a 64 bit segment

and a 128 bit segment. The 64 bit segment con-

tains a unique device number written by ST, while

the second one is one-time-programmable by the

user. The user programmable segment can be

permanently protected. Figure 6, shows the Pro-

tection Register Memory Map.

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards.

The memory is offered in TSOP48 (12 X 20mm)

and TFBGA48 (6.39 x 10.5mm, 0.75mm pitch)

packages and is supplied with all the bits erased

(set to ’1’).

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A21

Address Inputs

DQ0-DQ15

Data Input/Output

Chip Enable

Output Enable

Write Enable

Reset

Write Protect

VDD

Core Power Supply

VDDQ

Power Supply for

Input/Output

VPP

Optional Supply Voltage for

Fast Program & Erase

VSS

Ground

Not Connected Internally

AI04378b

A0-A21

DQ0-DQ15

VDD

M28W640ECT

M28W640ECB

VSS

VDDQ VPP

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