M29KW032E datasheet(13/30 Pages) STMICROELECTRONICS

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M29KW032E

STATUS REGISTER

Bus Read operations from any address always

read the Status Register during Program and

Erase operations. The bits in the Status Register

are summarized in Table 8, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion. The Data Polling Bit is output on DQ7 when

the Status Register is read.

During a Word Program operation the Data Polling

Bit outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Word Program operation the memory returns

to Read mode and Bus Read operations from the

address just programmed output DQ7, not its com-

plement. The Data Polling Bit is not available dur-

ing a Multiple Word Program operation.

During Erase operations the Data Polling Bit out-

puts ’0’, the complement of the erased state of

DQ7. After successful completion of the Erase op-

eration the memory returns to Read Mode.

Figure 6, Data Polling Flowchart, gives an exam-

ple of how to use the Data Polling Bit. A Valid Ad-

dress is the address being programmed or an

address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to

identify whether the Program/Erase Controller has

successfully completed its operation. The Toggle

Bit is output on DQ6 when the Status Register is

read.

During Program and Erase operations the Toggle

Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-

sive Bus Read operations at any address. After

successful completion of the operation the memo-

ry returns to Read mode.

Figure 7, Data Toggle Flowchart, gives an exam-

ple of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Error Bit is set to ’1’ when a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Read/Reset command must be issued

before other commands are issued. The Error bit

is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a

bit set to ’0’ back to ’1’ and attempting to do so will

set DQ5 to ‘1’. A Bus Read operation to that ad-

dress will show the bit is still ‘0’. One of the Erase

commands must be used to set all the bits in a

block or in the whole memory from ’0’ to ’1’.

VPP Status Bit (DQ4). The VPP Status Bit can be

used to identify if any Program or Erase operation

has failed due to a VPP error. If VPP falls below VHH

during any Program or Erase operation, the oper-

ation aborts and DQ4 is set to ‘1’. If VPP remains at

VHH throughout the Program or Erase operation,

the operation completes and DQ4 is set to ‘0’.

Erase Timer Bit (DQ3). The Erase Timer Bit can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing the Erase Timer Bit is set to ’1’. The Erase

Timer Bit is output on DQ3 when the Status Reg-

ister is read.

Alternative Toggle Bit (DQ2). The

Alternative

Toggle Bit can be used to monitor the Program/

Erase controller during Block and Chip Erase op-

erations. The Alternative Toggle Bit is output on

DQ2 when the Status Register is read.

During Erase operations the Toggle Bit changes

from ’0’ to ’1’ to ’0’, etc., with successive Bus Read

operations to any address. Once the operation

completes the memory returns to Read mode.

If an Erase operation fails and the Error Bit is set,

the Alternative Toggle Bit will continue to toggle

with successive Bus Read operations to any ad-

dress. The Alternative Toggle Bit does not change

if the addressed block has erased correctly.

Multiple Word Program Bit (DQ0). The Multiple

Word Program Bit can be used to indicate whether

the Program/Erase Controller is active or inactive

during Multiple Word Program. When the Pro-

gram/Erase Controller has written one Word and is

ready to accept the next Word, the bit is set to ‘0’.

Status Register Bit DQ1 is reserved.

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