M29KW032E

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Table 8. Status Register Bits

Note: 1. Unspecified data bits should be ignored.

2. DQ2 toggles on any address during Block or Chip Erase and after an Erase error.

Figure 6. Data Polling Flowchart

Figure 7. Data Toggle Flowchart

Operation

Condition

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ0

RB

Word Program

Any Address

DQ7

Toggle

0

––

–

–

0

Word Program

Error

DQ7

Toggle

1

0

–

–

–

0

DQ7

Toggle

1

1

–

–

–

0

Block/ Chip

Erase

Any Address

0

Toggle

0

–

1

–0

Erase Error

0

Toggle

1

0

1

–0

0

Toggle

1

1

1

–0

Multiple Word

Program

P/E.C. active

–

Toggle

0

–

–

–

1

0

P/E.C. inactive,

waiting for next

Word

–

Toggle

0

–

–

–

0

1

Multiple Word

Program

Error

–

Toggle

1

0

–

–

1

0

–

Toggle

1

1

–

–

1

0

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAIL

PASS

AI03598

DQ7

=

DATA

YES

NO

YES

NO

DQ5

= 1

DQ7

=

DATA

YES

NO

READ DQ6

START

READ DQ6

TWICE

FAIL

PASS

AI01370B

DQ6

=

TOGGLE

NO

NO

YES

YES

DQ5

= 1

NO

YES

DQ6

=

TOGGLE

READ

DQ5 & DQ6