M34S32

11/18

Example of an incorrect sequence, disabling the

Write in the OTP page:

Start

1010 0010

(OTP page select code)

Ack

xxxx 0000

(MSB address)

Ack

0000 0100

(incorrect LSB address)

Ack

(acknowledged, but...)

0100 1101

(the attempts at)

(no ack)

(writing data to the)

1100 1010

(OTP page are)

(no ack)

(not acknowledged)

0101 0011

(no ack)

Stop

Figure 10. Write Modes Sequence with WC = 0

and WCpol = 0

Note: 1. The device has the same behavior when WC = 1 and

WCpol = 1.

BYTE WRITE

DEV SEL

BYTE ADDR

BYTE ADDR

DATA IN

WC

PAGE WRITE

DEV SEL

BYTE ADDR

BYTE ADDR

DATA IN 1

WC

DATA IN 2

AI01106B

PAGE WRITE

(cont'd)

WC (cont'd)

DATA IN N

ACK

R/W

ACK

ACK

ACK

ACK

ACK

ACK

ACK

R/W

ACK

ACK

Minimizing System Delay by Polling On ACK.

During the internal Write cycle, the memory disa-

bles itself from the bus in order to copy the data

from the internal latches to the memory cells. The

the AC Characteristics table, this timing value may

be reduced by an ACK polling sequence issued by

the master.

The sequence is:

– Initial condition: a Write is in progress (see Fig-

ure 7).

– Step 1: the Master issues a START condition fol-

lowed by a Device Select Byte. (1st byte of the

new instruction)

– Step 2: if the memory is internally writing, no

ACK will be returned. The Master goes back to

Step1. If the memory has terminated the internal

writing, it will issue an ACK.

The memory is ready to receive the second part of

the instruction (the first byte of this instruction was

already sent during Step1).