M34S32 datasheet(4/18 Pages) STMICROELECTRONICS

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M34S32

Write Control (WC). The Write Control feature

WC is useful to protect the contents of the whole

EEPROM area from any erroneous erase/write cy-

cle. It also protects the OTP page against the first

write attempt. The Write Control signal polarity can

be selected with the WCpol bit of the Control Reg-

ister (see Table 13). When pin WC is unconnect-

ed, the WC input is internally read as VIL (see

Table 5).

When WC and WCpol are activating the Write Pro-

tection, Device Select and Address bytes are ac-

knowledged; Data bytes are not acknowledged

(see Figure 11).

Write Control (WCR). In order to prevent spurious

writes to the Control Register, the user can also

make the Control Register Read Only (Write is in-

hibited). This is achieved by use of the WCR pin

and the CRWD bit (see Table 14) :

– - if CRWD bit = 0, the Control register can be

modified regardless of the state of the WCR pin.

– - if CRWD bit = 1, the Control register can be

modified if the WCR pin is high.

– - if CRWD bit = 1 and the WCR pin is low, the

Control Register is Write Protected.

DEVICE OPERATION

I2C Bus Background

The memory supports the extended addressing

I2C protocol. This protocol defines any device that

sends data onto the bus as a transmitter and any

device that reads the data as a receiver. The de-

vice that controls the data transfer is known as the

master and the other as the slave. The master will

always initiate a data transfer and will provide the

serial clock for synchronisation. The memory is al-

ways a slave device in all communications.

Table 5. Input Parameters (1)

(TA = 25°C, f = 400 kHz)

Symbol

Parameter

Test Condition

Min.

Max.

Unit

CIN

Input Capacitance (SDA)

CIN

Input Capacitance (other pins)

WC, WCR Input Impedance

VIN ≤ 0.3 VCC

520

Ω

WC, WCR Input Impedance

VIN ≥ 0.7 VCC

500

Ω

tLP

Low-pass filter input time constant (SDA and SCL)

100

Note: 1. Sampled only, not 100% tested in production.

Start Condition. START is identified by a high to

low transition of the SDA line while the clock SCL

is stable in the high state. A START condition must

precede any command for data transfer. Except

during a programming cycle, the memory continu-

ously monitors the SDA and SCL signals for a

START condition and will not respond unless one

is given.

Stop Condition. STOP is identified by a low to

high transition of the SDA line while the clock SCL

is stable in the high state. A STOP condition termi-

nates communication between the memory and

the bus master. A STOP condition at the end of a

Read command forces the stand-by state. A

STOP condition at the end of a Write command

triggers the internal EEPROM write cycle.

Acknowledge Bit (ACK). An acknowledge signal

is used to indicate a successful data transfer. The

bus transmitter, either master or slave, will release

the SDA bus after sending 8 bits of data. During

the 9th clock pulse the receiver pulls the SDA bus

low to acknowledge the receipt of the 8 bits of da-

ta.

Data Input. During data input the memory sam-

ples the SDA bus signal on the rising edge of the

clock SCL. For correct device operation the SDA

signal must be stable during the clock low to high

transition and the data must change ONLY when

the SCL line is low.

Device Selection. To start communication be-

tween the bus master and the slave memory, the

master must initiate a START condition. The 8 bits

sent after a START condition are made up of a De-

vice Select Byte of 4 bits that identifies the device

type, 3 memory block access bits and one bit for a

READ (RW = 1) or WRITE (RW = 0) operation.

There are two modes both for read and write.

These are summarised in Table 4 and described

hereafter. Communication between the master

and the slave is ended with a STOP condition.

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