MSC8103RMSLASHD datasheet(101/104 Pages) FREESCALE

101 / 104 page

Layout Practices

MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

4-3

Since the address pins switch once at every second cycle, the address pins frequency is a quarter of the bus

frequency (that is, 25 MHz).

For the same reason the data pins frequency is 3.125 MHz.

Calculating internal power (from Table 2-5 values):

PCORE (200) = ((PCORE – PLCO)/300) × 200 + PLCO =((450 – 3) / 300 × 200 + 3 = 301

PCPM (100) = ((PCPM – PLCP) / 200) × 100 + PLCP = ((320 – 6) / 200) × 100 + 6 = 163

PSIU (50) = ((PSIU – PLSI) / 100) × 50 + PLSI = ((80 – 2) / 100) × 50 + 2 = 41

PINT = PCORE(200) + PCPM(100) + PSIU(50) = 301 + 163 + 41 = 505

PD = PINT + PI/O = 505 + 67 = 572

Maximum allowed ambient temperature is:

TA = TJ – (PD × θJA)

4.4 Layout Practices

Each VCC and VDD pin on the MSC8103 should be provided with a low-impedance path to the board’s power supply.

Similarly, each GND pin should be provided with a low-impedance path to ground. The power supply pins drive

distinct groups of logic on the chip. The VCC power supply should be bypassed to ground using at least four 0.1 µF

by-pass capacitors located as closely as possible to the four sides of the package. The capacitor leads and

associated printed circuit traces connecting to chip VCC, VDD, and GND should be kept to less than half an inch per

capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes.

All output pins on the MSC8103 have fast rise and fall times. Printed circuit board (PCB) trace interconnection

length should be minimized in order to minimize undershoot and reflections caused by these fast output switching

times. This recommendation particularly applies to the address and data busses. Maximum PCB trace lengths of six

inches are recommended. Capacitance calculations should consider all device loads as well as parasitic

capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes especially critical in

systems with higher capacitive loads because these loads create higher transient currents in the VCC, VDD, and GND

circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to

minimize the noise levels on the PLL supply pins.

There are 2 pairs of PLL supply pins: VCCSYN-GNDSYN and VCCSYN1-GNDSYN1. Each pair supplies one PLL. To

ensure internal clock stability, filter the power to the VCCSYN and VCCSYN1 inputs with a circuit similar to the one in

Figure 4-2. To filter as much noise as possible, place the circuit as close as possible to VCCSYN and VCCSYN1. The

0.01-µF capacitor should be closest to VCCSYN and VCCSYN1, followed by the 10-µF capacitor, the 10-nH inductor,

and finally the 10-

Ω resistor to V

DD. These traces should be kept short and direct.

Table 4-1.

Power Dissipation

Pins

Number of Pins

Switching

× C

× VDDH2

× f × 10–3

Power in mW

Address

Data, HRD, HRW

CLKOUT

× 30

× 3.32

× 12.5 × 10–3

× 3. 125 × 10–3

× 50 × 10–3

16.25

34.75

Total PI/O

MSC8103RM/D 数据表(PDF) 101 Page - Freescale Semiconductor, Inc

MSC8103RM/D 数据表(HTML) 101 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载