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MSC8103RM/D 数据表(PDF) 102 Page - Freescale Semiconductor, Inc |
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MSC8103RM/D 数据表(HTML) 102 Page - Freescale Semiconductor, Inc |
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102 / 104 page ![]() MSC8103 Network Digital Signal Processor, Rev. 11 4-4 Freescale Semiconductor Design Considerations GNDSYN and GNDSYN1 should be provided with an extremely low impedance path to ground and should be bypassed to VCCSYN and VCCSYN1, respectively, by a 0.01-µF capacitor located as close as possible to the chip package. The user should also bypass GNDSYN and GNDSYN1 to VCCSYN and VCCSYN1 with a 0.01-µF capacitor as closely as possible to the chip package Figure 4-2. VCCSYN and VCCSYN1 Bypass VDD 0.01 µF 10 µF VCCSYN 10 Ω 10nH |
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