AI01019

5V

OUT

CL = 100pF

CL includes JIG capacitance

1.8k

Ω

DEVICE

UNDER

TEST

1k

Ω

Figure 4. AC Testing Load Circuit

Input Rise and Fall Times

≤ 5ns

Input Pulse Voltages

0V to 3V

Input and Output Timing Ref. Voltages

1.5V

Note that Output Hi-Z is defined as the point where data is no

longer driven.

Table 4. AC Measurement Conditions

AI01329

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

VPFD

VCC

VSS

32,768 Hz

CRYSTAL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

8 x 8 BiPORT

SRAM ARRAY

2040 x 8

SRAM ARRAY

A0-A10

DQ0-DQ7

E

W

G

POWER

BOK

Figure 3. Block Diagram

Byte 7F8h is the clock control register. This byte

controls user access to the clock information and

also stores the clock calibration setting.

The eight clock bytes are not the actual clock

counters themselves; they are memory locations

consisting of BiPORT

™ read/write memory cells.

The M48T02/12 includes a clock control circuit

which updates the clock bytes with current informa-

tion once per second. The information can be

accessed by the user in the same manner as any

other location in the static memory array.

The M48T02/12 also has its own Power-fail Detect

circuit. The control circuitry constantlymonitors the

single 5V supply for an out of tolerance condition.

protects the SRAM, providing a high degree of data

security in the midst of unpredictable system op-

approximately3V, the control circuitry connectsthe

battery which maintains data and clock operation

until valid power returns.

3/15

M48T02, M48T12