M48T58 datasheet(9/17 Pages) STMICROELECTRONICS

9 / 17 page

The eight clock bytes are not the actual clock

counters themselves; they are memory locations

consisting of BiPORT

™ read/write memory cells.

The M48T58/58Y includes a clock control circuit

which updates the clock bytes with current informa-

tion once per second.

The information can be

accessed by the user in the same manner as any

other location in the static memory array.

The M48T58/58Y also has its own Power-fail De-

tect circuit. The control circuitry constantly monitors

the single 5V supply for an out of tolerance condi-

tion. When VCC is out of tolerance, the circuit write

protects the SRAM, providing a high degree of data

security in the midst of unpredictable system op-

eration brought on by low VCC. As VCC falls below

approximately 3V, the control circuitry connects the

battery which maintains data and clock operation

until valid power returns.

READ MODE

The M48T58/58Y is in the Read Mode whenever

W (Write Enable) is high, E1 (Chip Enable 1) is low,

and E2 (Chip Enable 2) is high. The unique address

specified by the 13 Address Inputs defines which

one of the 8,192 bytes of data is to be accessed.

Valid data will be available at the Data I/O pins

within Address Access time (tAVQV) after the last

address input signal is stable, providing that the E1,

E2, and G access times are also satisfied. If the E1,

E2 and G access times are not met, valid data will

be available after the latter of the Chip Enable

Access times (tE1LQV or tE2HQV) or Output Enable

Access time (tGLQV).

The state of the eight three-state Data I/O signals

is controlled by E1, E2 and G. If the outputs are

activated before tAVQV, the data lines will be driven

to an indeterminate state until tAVQV. If the Address

Inputs are changed while E1, E2 and G remain

active, output data will remain valid for Output Data

Hold time (tAXQX) but will go indeterminate until the

next Address Access.

WRITE MODE

The M48T58/58Y is in the Write Mode whenever W

and E1 are low and E2 is high. The start of a write

is referenced from the latter occurring falling edge

of W or E1, or the rising edge of E2. A write is

terminated by the earlier rising edge of W or E1, or

the falling edge of E2. The addresses must be held

valid throughout the cycle. E1 or W must return high

or E2 low for a minimum of tE1HAX or tE2LAX from

Chip Enable or tWHAX from Write Enable prior to the

initiation of another read or write cycle. Data-in

must be valid tDVWH prior to the end of write and

remain valid for tWHDX afterward. G should be kept

high during write cycles to avoid bus contention;

although, if the output bus has been activated by a

low on E1 and G and a high on E2, a low on W will

disable the outputs tWLQZ after W falls.

DESCRIPTION (cont’d)

Address

Data

Function/Range

BCD Format

1FFFh

10 Years

Year

00-99

1FFEh

10 M.

Month

01-12

1FFDh

10 Date

Date

01-31

1FFCh

Day

01-07

1FFBh

10 Hours

Hours

Hour

00-23

1FFAh

10 Minutes

Minutes

00-59

1FF9h

10 Seconds

Seconds

00-59

1FF8h

Calibration

Control

Keys: S = SIGN Bit

FT = FREQUENCY TEST Bit (Must be set to ’0’ upon power, for normal clock operation)

R = READ Bit

W = WRITE Bit

ST = STOP Bit

= Must be set to ’0’

Table 11. Register Map

9/17

M48T58, M48T58Y

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