Symbol

Parameter

Test Condition

Min

Max

Unit

(1)

Input Leakage Current

0V

±1

µA

(1)

Output Leakage Current

0V

±5

µA

Supply Current

Outputs open

50

mA

Supply Current (Standby) TTL

3mA

Supply Current (Standby) CMOS

3mA

(2)

Input Low Voltage

–0.3

0.8

V

Input High Voltage

2.2

V

Output Low Voltage

0.4

V

Output Low Voltage (FT)

(3)

0.4

V

Output High Voltage

2.4

V

Notes: 1. Outputs Deselected.

2. Negative spikes of –1V allowed for up to 10ns once per Cycle.

3. The FT pin is Open Drain.

Table 6. DC Characteristics

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Capacitance

10

pF

(3)

Input / Output Capacitance

10

pF

Notes: 1. Effective capacitance measured with power supply at 5V.

2. Sampled only, not 100% tested.

3. Outputs deselected

°C, f = 1 MHz )

Symbol

Parameter

Min

Typ

Max

Unit

Power-fail Deselect Voltage (M48T58)

4.5

4.6

4.75

V

Power-fail Deselect Voltage (M48T58Y)

4.2

4.35

4.5

V

Battery Back-up Switchover Voltage

3.0

V

(2)

Expected Data Retention Time

7

YEARS

2. At 25°C

°C)

For the 28 lead SOIC, the battery/crystal package

( i.e. SNA PHAT ) p art num ber is "M 4T28-

BR12SH1".

As Figure 3 shows, the static memory array and the

q ua r t z co nt rol led clock o sci lla t or of t h e

M48T58/58Y are integrated on one silicon chip.

The two circuits are interconnected at the upper

eight memory locations to provide user accessible

BYTEWIDE

™ clock information in the bytes with

addresses 1FF8h-1FFFh. The clock locations con-

tain the year, month, date, day, hour, minute, and

second in 24 hour BCD format. Corrections for 28,

29 (leap year), 30, and 31 day months are made

automatically. Byte 1FF8h is the clock control reg-

ister. This byte controls user access to the clock

information and also stores the clock calibration

setting.

DESCRIPTION (cont’d)

4/17

M48T58, M48T58Y