M48T86PC datasheet(8/23 Pages) STMICROELECTRONICS

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M48T86

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Table 7. Power Down/Up Trip Points DC Characteristics (1)

(TA = 0 to 70 °C)

Note: 1. All voltages referenced to VSS.

2. At 25°C.

Table 8. Power Down/Up Mode AC Characteristics

(TA = 0 to 70°C)

Note: 1. VCC fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD.

Symbol

Parameter

Min

Typ

Max

Unit

VPFD

Power-fail Deselect Voltage

4.0

4.35

VSO

Battery Back-up Switchover Voltage

3.0

tDR

(2)

Expected Data Retention Time

YEARS

Symbol

Parameter

Min

Max

Unit

(1)

VCC Fall Time

300

µs

VCC Rise Time

100

µs

tREC

VPFD to E High

200

Figure 7. Power Down/Up Mode AC Waveforms

AI01646

VCC

tREC

4.5V

VPFD

VSO

INTERRUPTS

The RTC plus RAM includes three separate, fully

automatic sources of interrupt (alarm, periodic, up-

date-in-progress) available to a processor. The

alarm interrupt can be programmed to occur at

rates from once per second to once per day. The

periodic interrupt can be selected from rates of

500ms to 122µs. The update-ended interrupt can

be used to indicate that an update cycle has com-

pleted.

The processor program can select which inter-

rupts, if any, are going to be used. Three bits in

to an interrupt-enable bit (Register B; Bit 6 = PIE;

Bit 5 = AIE; Bit 4 = UIE) permits an interrupt to be

initialized when the event occurs. A zero in an in-

terrupt-enable bit prohibits the IRQ pin from being

asserted from that interrupt condition. If an inter-

rupt flag is already set when an interrupt is en-

abled, IRQ is immediately set at an active level,

although the interrupt initiating the event may have

occurred much earlier. As a result, there are cases

where the program should clear such earlier initi-

ated interrupts before first enabling new interrupts.

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