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M48T86

Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other conditions above those indicated in the operational section

of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect

reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.

CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

0 to 70

°C

–40 to 85

°C

(2)

Lead Solder Temperature for 10 seconds

260

°C

Input or Output Voltages

–0.3 to 7.0

V

Supply Voltage

–0.3 to 7.0

V

Power Dissipation

1

W

For the 28 lead SOIC, the battery/crystal package

part number is "M4T28-BR12SH1".

Automatic deselection of the device provides in-

surance that data integrity is not compromised

tion of the device remains in effect upon power up

and the count down chain is not reset. This allows

system clock a wake up period so that a valid sys-

tem reset can be established.

The block diagram in Figure 3 shows the pin con-

nections and the major internal functions of the

M48T86.

SIGNAL DESCRIPTION

SQW (Square Wave Output). During normal op-

signal from one of 13 taps.The frequency of the

SQW pin can be changed by programming Regis-

ter A as shown in Table 10. The SQW signal can

be turned on and off using the SQWE bit (Register

B; bit 3). The SQW signal is not available when

AD0-AD7 (Multiplexed Bi-Directional Address/

Data Bus). The M48T86 provides a multiplexed

bus in which address and data information share

the same signal path. The bus cycle consists of

two stages; first the address is latched, followed by

the data. Address/Data multiplexing does not slow

the access time of the M48T86, since the bus

change from address to data occurs during the in-

ternal RAM access time. Addresses must be valid

prior to the falling edge of AS, at which time the

M48T86 latches the address present on AD0-

AD7. Valid write data must be present and held

stable during the latter portion of the R/W pulse. In

a read cycle, the M48T86 outputs 8 bits of data

during the latter portion of the DS pulse. The read

cycle is terminated and the bus returns to a high

impedance state upon a high transition on R/W.

AS (Address Strobe Input). A

positive

going

pulse on the Address Strobe (AS) input serves to

demultiplex the bus. The falling edge of AS causes

the address present on AD0-AD7 to be latched

within the M48T86.

MOT (Mode Select). The MOT pin offers the flex-

ibility to choose between two bus types. When

bus timing is selected. The pin has an internal pull-

down resistance of approximately 20K ohms.