M48T86PC datasheet(12/23 Pages) STMICROELECTRONICS

12 / 23 page

M48T86

12/23

UPDATE CYCLE INTERRUPT

After each update cycle, the update cycle ended

flag bit (UF) (Register C; Bit 4) is set to a "1". If the

update interrupt enable bit (UIE) (Register B; Bit 4)

is set to a "1", and the SET bit (Register B; Bit 7) is

a "0", then an interrupt request is generated at the

end of each update cycle.

SQUARE WAVE OUTPUT SELECTION

Thirteen of the 15 divider taps are made available

to a 1-of-15 selector, as shown in the block dia-

gram of Figure 3. The purpose of selecting a divid-

er tap is to generate a square wave output signal

on the SQW pin. The RS3-RS0 bits in Register A

establish the square wave output frequency.

These frequencies are listed in Table 10. The

SQW frequency selection shares the 1-of-15 se-

lector with the periodic interrupt generator. Once

the frequency is selected, the output of the SQW

pin can be turned on and off under program control

with the square wave enabled (SQWE).

OSCILLATOR CONTROL BITS

When the M48T86 is shipped from the factory the

internal oscillator is turned off. This feature pre-

vents the lithium energy cell from being dis-

charged until it is installed in a system. A pattern of

"010" in Bits 4-6 of Register A will turn the oscilla-

tor on and enable the countdown chain. A pattern

of "11X" will turn the oscillator on, but holds the

countdown chain of the oscillator in reset. All other

combinations of Bits 4-6 keep the oscillator off.

Figure 11. Address Map

AI01650

SECONDS

SECONDS ALARM

MINUTES

MINUTES ALARM

HOURS

HOURS ALARM

DAY OF WEEK

DATE OF MONTH

MONTH

YEAR

BCD OR

BINARY

FORMAT

127

114

BYTES

CLOCK AND CONTROL

STATUS REGISTERS

STORAGE REGISTERS

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