M50LPW012 datasheet(7/35 Pages) STMICROELECTRONICS

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M50LPW012

Note that, during a Bus Write operation, the

Command

Interface

starts

executing

the

command as soon as the data is fully received; a

Bus Abort during the final TAR cycles is not

guaranteed to abort the command; the bus,

however, will be released immediately.

Standby. When LFRAME is High, VIH, the

memory is put into Standby mode where LAD0-

LAD3 are put into a high-impedance state and the

Supply Current is reduced to the Standby level,

ICC1.

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high-impedance. The memory is

in Reset mode when Interface Reset, RP, or CPU

Reset, INIT, is Low, VIL. RP or INIT must be held

Low, VIL, for tPLPH. The memory resets to Read

mode upon return from Reset mode and the Lock

Registers return to their default states regardless

of their state before Reset, see Table 16. If RP or

INIT goes Low, VIL, during a Program or Erase

operation, the operation is aborted and the

memory cells affected no longer contain valid

data; the memory can take up to tPLRH to abort a

Program or Erase operation.

Block Protection. Block

Protection

can

forced using the signals Top Block Lock, TBL, and

Write Protect, WP, regardless of the state of the

Lock Registers.

Address/Address Multiplexed (A/A Mux) Bus

Operations

The Address/Address Multiplexed (A/A Mux)

Interface has a more traditional style interface.

The signals consist of a multiplexed address

signals (A0-A10), data signals, (DQ0-DQ7) and

three control signals (RC, G, W). An additional

signal, RP, can be used to reset the memory.

The Address/Address Multiplexed (A/A Mux)

Interface

included

for

use

Flash

Programming

equipment

for

faster

factory

programming. Only a subset of the features

available to the Low Pin Count (LPC) Interface are

available; these include all the Commands but

exclude the Security features and other registers.

The following operations can be performed using

the appropriate bus cycles: Bus Read, Bus Write,

Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux)

Interface

selected

all

the

blocks

are

unprotected. It is not possible to protect any blocks

through this interface.

Bus Read. Bus Read operations are used to

output the contents of the Memory Array, the

Electronic Signature and the Status Register. A

valid Bus Read operation begins by latching the

Row Address and Column Address signals into

the memory using the Address Inputs, A0-A10,

and the Row/Column Address Select RC. Then

Write Enable (W) and Interface Reset (RP) must

be High, VIH, and Output Enable, G, Low, VIL, in

order to perform a Bus Read operation. The Data

Inputs/Outputs will output the value, see Figure

11, A/A Mux Interface Read AC Waveforms, and

Table

25,

A/A

Mux

Interface

Read

Characteristics, for details of when the output

becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by latching the Row Address and Column

Address signals into the memory using the

Address Inputs, A0-A10, and the Row/Column

Address Select RC. The data should be set up on

the Data Inputs/Outputs; Output Enable, G, and

Interface Reset, RP, must be High, VIH and Write

Enable, W, must be Low, VIL. The Data Inputs/

Outputs are latched on the rising edge of Write

Enable, W. See Figure 12, A/A Mux Interface

Write AC Waveforms, and Table 26, A/A Mux

Interface Write AC Characteristics, for details of

the timing requirements.

Output Disable. The data outputs are high-im-

pedance when the Output Enable, G, is at VIH.

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high-impedance. The memory is

in Reset mode when RP is Low, VIL. RP must be

held Low, VIL for tPLPH. If RP is goes Low, VIL,

during

Program or

Erase

operation, the

operation is aborted and the memory cells affected

no longer contain valid data; the memory can take

up to tPLRH to abort a Program or Erase operation.

Table 6. Block Addresses

Note: For A19:18 values, refer to Table 2.

Size

(KBytes)

Address Range

Block

Number

Block Type

3C000h-3FFFFh

Boot Block

3A000h-3BFFFh

Parameter

Block

38000h-39FFFh

Parameter

Block

30000h-37FFFh

Main Block

20000h-2FFFFh

Main Block

10000h-1FFFFh

Main Block

00000h-0FFFFh

Main Block

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