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M50LPW012

Table 27. Ordering Information Scheme

For a list of available options or for further information on any aspect of this device, please contact the ST

Sales Office nearest to you.

Example:

M50LPW012

K

1

T

Device Type

M50

Architecture

LP = Low Pin Count Interface

Operating Voltage

W = 3.0 to 3.6V

Device Function

012 = 2 Mbit (256Kb x8), Boot Block

Package

K = PLCC32

Temperature Range

1 = 0 to 70 °C

Option

T = Tape & Reel Packing

Table 28. Revision History

Date

Version

Revision Details

17-Jun-2002

-01

First Issue

29-Aug-2002

1.1

PC Chipsets without automapping memory features mentioned on page 1

16-Sep-2002

1.2

Register Configuration Map) for Bottom Boot Block devices