M50LPW040

28/36

Figure 15. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)

mand sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

3. Address 1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1.

AI03982

Write Address 4

& Data 4 (3)

Read Status

Register

YES

NO

b7 = 1

YES

NO

b3 = 0

NO

b4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

Quadruple Byte Program command:

– write 30h

– write Address 1 & Data 1 (3)

– write Address 2 & Data 2 (3)

– write Address 3 & Data 3 (3)

– write Address 4 & Data 4 (3)

(memory enters read status state after

the Quadruple Byte Program command)

do:

– read Status Register if Program/Erase

Suspend command given execute

suspend program loop

while b7 = 1

If b3 = 1, VPP invalid error:

– error handler

If b4 = 1, Program error:

– error handler

End

YES

Suspend

Suspend

Loop

NO

YES

Write 30h

Start

Write Address 1

& Data 1 (3)

Write Address 2

& Data 2 (3)

Write Address 3

& Data 3 (3)