M50LPW116 datasheet(11/36 Pages) STMICROELECTRONICS

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M50LPW116

command is issued subsequent Bus Read opera-

tions read the Status Register until another com-

mand is issued. See the section on the Status

Read Electronic Signature Command. The Read

Electronic Signature command is used to read the

Manufacturer Code and the Device Code. One

Bus Write cycle is required to issue the Read

Electronic

Signature

command.

Once

the

command

issued

subsequent

Bus

Read

operations read the Manufacturer Code or the

Device Code until another command is issued.

After the Read Electronic Signature Command is

issued the Manufacturer Code and Device Code

can be read using Bus Read operations using the

addresses in Table 10.

Program Command. The

Program

command

can be used to program a value to one address in

the memory array at a time. Two Bus Write

operations are required to issue the command; the

second Bus Write cycle latches the address and

data in the internal state machine and starts the

Program/Erase Controller. Once the command is

issued subsequent Bus Read operations read the

Status Register. See the section on the Status

If the address falls in a protected block then the

Program operation will abort, the data in the

memory array will not be changed and the Status

During the Program operation the memory will

only accept the Read Status Register command

and the Program/Erase Suspend command. All

other commands will be ignored. Typical Program

times are given in Table 12.

Note that the Program command cannot change a

bit set at ‘0’ back to ‘1’ and attempting to do so will

not cause any modification on its value. One of the

Erase commands must be used to set all of the

bits in the block to ‘1’.

See Figure 13, for a suggested flowchart on using

the Program command.

Quadruple Byte Program Command (A/A Mux

Mode). The Quadruple Byte Program Command

can be used to program four adjacent bytes in the

memory array at a time. The four bytes must differ

only for the addresses A0 and A1. Programming

should not be attempted when VPP is not at VPPH.

Five Bus Write operations are required to issue the

command. The second, the third and the fourth

Bus Write cycle latches respectively the address

and data of the first, the second and the third byte

in the internal state machine. The fifth Bus Write

cycle latches the address and data of the fourth

byte in the internal state machine and starts the

Program/Erase Controller. Once the command is

issued subsequent Bus Read operations read the

Status Register. See the section on the Status

During the Quadruple Byte Program operation the

memory will only accept the Read Status register

command and the Program/Erase Suspend com-

mand. All other commands will be ignored. Typical

Quadruple Byte Program times are given in Table

12.

Note that the Quadruple Byte Program command

cannot change a bit set to ‘0’ back to ‘1’ and

attempting to do so will not cause any modification

on its value. One of the Erase commands must be

used to set all of the bits in the block to ‘1’.

See Figure 14, for a suggested flowchart on using

the Quadruple Byte Program command.

Chip Erase Command. The Chip Erase Com-

mand can be only used in A/A Mux mode to erase

the entire chip at a time. Erasing should not be at-

tempted when VPP is not at VPPH. The operation

can also be executed if VPP is below VPPH, but re-

sult could be uncertain. Two Bus Write operations

are required to issue the command and start the

Program/Erase Controller. Once the command is

issued subsequent Bus Read operations read the

Status Register. See the section on the Status

memory will only accept the Read Status Register

command. All other commands will be ignored.

Typical Chip Erase times are given in Table 12.

The Chip Erase command sets all of the bits in the

memory to ‘1’. See Figure 16, Chip Erase Flow-

chart and Pseudo Code (A/A Mux Interface Only),

for a suggested flowchart on using the Chip Erase

command.

Block Erase Command. The Block Erase com-

mand can be used to erase a block. Two Bus Write

operations are required to issue the command; the

second Bus Write cycle latches the block address

in the internal state machine and starts the Pro-

gram/Erase Controller. Once the command is is-

sued subsequent Bus Read operations read the

Status Register. See the section on the Status

If the block is protected then the Block Erase

operation will abort, the data in the block will not be

Table 10. Read Electronic Signature

Code

Address

Data

Manufacturer Code

000000h

20h

Device Code

000001h

30h

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