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M50LPW116

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs hold the data that is written to or read

from the memory. They output the data stored at

the selected address during a Bus Read opera-

tion. During Bus Write operations they represent

the commands sent to the Command Interface of

the internal state machine. The Data Inputs/Out-

puts, DQ0-DQ7, are latched during a Bus Write

operation.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

Row/Column Address Select (RC). The

Row/

Column Address Select input selects whether the

Address Inputs should be latched into the Row

Address bits (A0-A10) or the Column Address bits

(A11-A20). The Row Address bits are latched on

the falling edge of RC whereas the Column

Address bits are latched on the rising edge.

Ready/Busy Output (RB). The Ready/Busy pin

gives the status of the memory’s Program/Erase

Controller. When Ready/Busy is Low, VOL, the

memory is busy with a Program or Erase operation

and it will not accept any additional Program or

Erase

command

except

the

Program/Erase

Suspend command. When Ready/Busy is High,

VOH, the memory is ready for any Read, Program

or Erase operation.

Supply Signal Descriptions

The Supply Signals are the same for both interfac-

es.

VCC Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is disabled when the VCC

Supply Voltage is less than the Lockout Voltage,

VLKO. This prevents Bus Write operations from

accidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the

memory contents being altered will be invalid.

After VCC becomes valid the Command Interface

is reset to Read mode.

A 0.1µF capacitor should be connected between

the VCC Supply Voltage pins and the VSS Ground

pin to decouple the current surges from the power

supply. Both VCC Supply Voltage pins must be

connected to the power supply. The PCB track

widths must be sufficient to carry the currents

required during program and erase operations.

Table 3. Signal Names (A/A Mux Interface)

Interface Configuration

A0-A10

Address Inputs

DQ0-DQ7

Data Inputs/Outputs

Output Enable

Write Enable

Row/Column Address Select

Ready/Busy Output

Interface Reset

VCC

Supply Voltage

VPP

Optional Supply Voltage for Fast

Program and Fast Erase Operations

VSS

Ground

Not Connected Internally

Write Protect (WP). The Write Protect input is

used to prevent the Blocks 0 to 48 from being

changed. When Write Protect, WP, is set Low, VIL,

Program and Block Erase operations in the Blocks

0 to 48 have no effect, regardless of the state of

the Lock Register. When Write Protect, WP, is set

High, VIH, the protection of the Block is determined

by the Lock Register. The state of Write Protect,

WP, does not affect the protection of the Top Block

(Block 49).

Write Protect, WP, must be set prior to a Program

or Block Erase operation is initiated and must not

be changed until the operation completes or un-

predictable results may occur. Care should be tak-

en to avoid unpredictable behavior by changing

WP during Program or Erase Suspend.

Reserved for Future Use (RFU). These pins do

not have assigned functions in this revision of the

part. They must be left disconnected.

Address/Address Multiplexed (A/A Mux)

Signal Descriptions

For the Address/Address Multiplexed (A/A Mux)

Interface see Figure 2, Logic Diagram (A/A Mux

Interface), and Table 3, Signal Names (A/A Mux

Interface).

Address Inputs (A0-A10). The Address Inputs

are used to set the Row Address bits (A0-A10) and

the Column Address bits (A11-A20). They are

latched during any bus operation by the Row/Col-

umn Address Select input, RC.

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