M50LPW116 datasheet(18/36 Pages) STMICROELECTRONICS

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M50LPW116

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Lock Registers

The Lock Registers control the protection status of

the Blocks. Each Block has its own Lock Register.

Blocks 0 to 15 have the same Lock Register.

Three bits within each Lock Register control the

protection of each block, the Write Lock Bit, the

Read Lock Bit and the Lock Down Bit.

The Lock Registers can be read and written,

though care should be taken when writing as, once

the Lock Down Bit is set, ‘1’, further modifications

to the Lock Register cannot be made until cleared,

to ‘0’, by a reset or power-up.

See Table 15 for details on the bit definitions of the

Lock Registers.

Write Lock. The

Write

Lock

Bit

determines

whether the contents of the Block can be modified

(using the Program or Block Erase Command).

When the Write Lock Bit is set, ‘1’, the block is

write protected; any operations that attempt to

change the data in the block will fail and the Status

Bit is reset, ‘0’, the block is not write protected

through the Lock Register and may be modified

unless write protected through some other means.

When VPP is less than VPPLK all blocks are pro-

tected and cannot be modified, regardless of the

state of the Write Lock Bit. If Top Block Lock, TBL,

is Low, VIL, then the Top Block (Block 49) is write

protected and cannot be modified. Similarly, if

Write Protect, WP, is Low, VIL, then the Blocks 0

to 48 are write protected and cannot be modified.

After power-up or reset the Write Lock Bit is al-

ways set to ‘1’ (write protected).

Read Lock. The

Read

Lock

bit

determines

whether the contents of the Block can be read

(from Read mode). When the Read Lock Bit is set,

‘1’, the block is read protected; any operation that

attempts to read the contents of the block will read

00h instead. When the Read Lock Bit is reset, ‘0’,

read operations in the Block return the data pro-

grammed into the block as expected.

After power-up or reset the Read Lock Bit is al-

ways reset to ‘0’ (not read protected).

Lock Down. The Lock Down Bit provides a

mechanism for protecting software data from sim-

ple hacking and malicious attack. When the Lock

Down Bit is set, ‘1’, further modification to the

Write Lock, Read Lock and Lock Down Bits cannot

be performed. A reset or power-up is required be-

fore changes to these bits can be made. When the

Lock Down Bit is reset, ‘0’, the Write Lock, Read

Lock and Lock Down Bits can be changed.

General Purpose Input Register

The General Purpose Input Register holds the

state of the General Purpose Input pins, GPI0-

GPI4. When this register is read, the state of these

pins is returned. This register is read-only and writ-

ing to it has no effect.

The signals on the General Purpose Input pins

should remain constant throughout the whole Bus

Read cycle in order to guarantee that the correct

data is read.

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