TPS73601DBVT datasheet(21/49 Pages) TI2

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The maximum power dissipated in the linear regulator is the maximum voltage dropped across the pass

transistor from the input to the output times the maximum load current. In this example, the maximum voltage

drop across in the pass transistor is 5V + 3% (5.15 V) minus 2.5V – 1% (2.475V) or 2.675V. The power

dissipated in the pass transistor is calculated by taking this voltage drop multiplied by the maximum load current.

For this example, the maximum power dissipated in the linear regulator is 1.07W. Once the power dissipated

in the linear regulator is known, the corresponding junction temperature rise can be calculated. To calculate the

junction temperature rise above ambient, the power dissipated must be multiplied by the junction-to-ambient

thermal resistance. For thermal resistance information, see the Thermal Information table. For this example,

using the DRB package, the maximum junction temperature rise is calculated to be 51°C. The maximum junction

temperature rise is calculated by adding junction temperature rise to the maximum ambient temperature. In this

example, the maximum junction temperature is 106°C. Keep in mind the maximum junction temperate must be

below 125°C for reliable operation. Addition ground planes, added thermal vias, and air flow all help to lower the

maximum junction temperature. Using the DCQ or DBV packages are not recommended for this application due

to the excessive junction temperature rise that is incurred.

R1 and R2 can be calculated for any output voltage using the formula shown in Figure 7-2. Sample resistor

values for common output voltages are shown in Figure 6-2.

For best accuracy, make the parallel combination of R1 and R2 approximately equal to 19kΩ. This 19kΩ, in

addition to the internal 8kΩ resistor, presents the same impedance to the error amplifier as the 27kΩ bandgap

reference output. This impedance helps compensate for leakages into the error amplifier terminals.

Using the values in Figure 6-2 for a 2.5V output results in a value of 39.2kΩ for R1 and 36.5kΩ for R2.

To get the noise level below 35µVRMS, a noise reduction capacitance (CFF) of 10nF is selected. Figure 5-47 must

be used as a reference when selecting optimal value for CFF.

A 10µF, low equivalent series resistance (ESR) ceramic X5R capacitor was used on the output of this design

to minimize the output voltage droop during a low transient. Use of an input capacitor is optional. However, in

systems where the input supply is located several inches away from the LDO, a small 0.1µF input capacitor is

recommended to negate the adverse effects that input supply inductance has on stability and ac performance.

See the Input and Output Capacitor Requirements section for additional information about input and output

capacitor selection.

7.2.2.1 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1μF to

1μF, low ESR capacitor across the input supply near the regulator. This capacitor counteracts reactive input

sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor can be

necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the

power source.

The TPS736 does not require an output capacitor for stability and has maximum phase margin with no capacitor.

The device is designed to be stable for all available types and values of capacitors. In applications where

multiple low ESR capacitors are in parallel, ringing can occur when the product of COUT and total ESR drops

below 50nΩ × F. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket,

and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance meets this

requirement.

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TPS736

SBVS038X – SEPTEMBER 2003 – REVISED MAY 2025

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