APM32F003F6P6-R datasheet(38/56 Pages) GEEHY

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Figure 10 SPI timing diagram—slave mode and CPHA=1(1)

NSS Input

MISO

Output

CPHA=1

CPOL=0

CPHA=1

MSB out

BIT 6~1 OUT

LSB OUT

LSB IN

Msb in

BIT 6~1 IN

tc(SCK)

th(SI)

tSU(SI)

th(NSS)

MOSI Input

CPOL=1

SCK Input

tSU(NSS)

tW(SCKH)

tW(SCKL)

ta(SO)

tV(SO)

th(SO)

tf(SCK)

tr(SCK)

tdls(SO)

Note: The measuring points are set at CMOS levels: 0.3VDD and 0.7VDD.

Figure 11 SPI timing diagram-main mode (1)

High

NSS input

MOSI

output

MISO input

MSB IN

MSB OUT

BIT 6~1 IN

LSB IN

LSB OUT

BIT 6~1 OUT

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1

tc(SCK)

th(MI)

tv(MO)

th(MO)

SCK input

tW(SCKH)

tW(SCKL)

tSU(MI)

tr(SCK)

tf(SCK)

Note: the measuring points are set at CMOS levels: 0.3 VDD and 0.7 VDD.

ADC characteristics

Table 4212-bit ADC features

Symbol

Parameter

Condition

Min

Typ

Max

Unit

VDD

Service voltage

2.4

5.5

fADC

ADC frequency

0.6

MHz

CADC

Internal sampling

and holding capacitance

RADC

Sampling resistance

1000

ohm

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