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AM261...ZFG 数据表(PDF) 185 Page - Texas Instruments |
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AM261...ZFG 数据表(HTML) 185 Page - Texas Instruments |
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185 / 218 page  6.11.6.2 Trace 6.11.6.2.1 Debug Trace Timing Conditions PARAMETER MIN MAX UNIT OUTPUT CONDITIONS CL Output Load Capacitance 2 5 pF OUTPUT CONDITIONS td(Trace Mismatch) Propagation delay mismatch across all traces. 200 ps 6.11.6.2.2 Debug Trace Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT DBTR1 tc(TRC_CLK) Cycle time, TRC_CLK 9.75 ns DBTR2 tw(TRC_CLKH) Pulse width, TRC_CLK high 4.13 ns DBTR3 tw(TRC_CLKL) Pulse width, TRC_CLK low 4.13 ns DBTR4 tosu(TRC_DATAV-TRC_CLK) Output setup time, TRC_DATA valid to TRC_CLK edge 1.22 ns DBTR5 toh(TRC_CLK-TRC-DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid 1.22 ns DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge 1.22 ns DBTR7 toh(TRC_CLK-TRC_CTLI) Output hold time, TRC_CLK edge to TRC_CTL invalid 1.22 ns TRC_DATA TRC_CTL TRC_CLK ( ) ( ) (Ideal) Worst Case 1 Worst Case 2 DBTR1 DBTR2 DBTR3 DBTR4 DBTR6 DBTR5 DBTR7 DBTR4 DBTR6 DBTR5 DBTR7 SPRSP08_Debug_01 Figure 6-88. Trace Switching Characteristics 6.12 Decoupling Capacitor Requirements 6.12.1 Decoupling Capacitor Requirements PARAMETER DESCRIPTION MIN TYP MAX UNIT CVDD 1.2V/1.25V VDD (Cap) 10 µF CVDDS33 3.3V VDDS (Cap) 10 µF CVDDA33 3.3V VDDA (Cap) 10 µF CVDDS18 1.8V VDDS (Cap) 0.1 µF CVDDA18 1.8V VDDA (Cap) 0.1 µF CVDDA18 1.8V VDDA (Cap) 4.7 µF CVPP 1.7V VPP (Cap) 0.1 µF CVDDS18_LDO 1.8V LDO VDDS (Cap) 3.3 µF CADC_VREF ADC VREFHI (Cap) 4.7 µF www.ti.com AM2612, AM2611, AM2611-Q1, AM2612-Q1 SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 185 Product Folder Links: AM2612 AM2611 AM2611-Q1 AM2612-Q1 |
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