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M58LW032D

Table 29. Extended Query information

Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV.

Address

Data (Hex)

Description

offset

x16

(P)h

0031h

62h

50h

"P"

Query ASCII string - Extended Table

(P+1)h

0032h

64h

52h

"R"

(P+2)h

0033h

66h

49h

"Y"

(P+3)h

0034h

68h

31h

Major version number

(P+4)h

0035h

6Ah

31h

Minor version number

(P+5)h

0036h

6Ch

CEh

Optional Feature: (1=yes, 0=no)

bit0, Chip Erase Supported (0=no)

bit1, Suspend Erase Supported (1=yes)

bit2, Suspend Program Supported (1=yes)

bit3, Protect/Unprotect Supported (1=yes)

bit4, Queue Erase Supported (0=no)

bit5, Instant Individual Block locking (0=no)

bit6, Protection bits supported (1=yes)

bit7, Page Read supported (1=yes)

bit8, Synchronous Read supported (0 =no)

bits 9 to 31 reserved for future use

(P+6)h

0037h

6Eh

00h

(P+7)h

0038h

70h

00h

(P+8)h

0039h

72h

00h

(P+9)h

003Ah

74h

01h

Function allowed after Suspend:

Program allowed after Erase Suspend (1=yes)

Bits 7-1 reserved for future use

(P+A)h

003Bh

76h

01h

Block Status Register

bit0, Block Protect Bit status active (1=yes)

bit1, Block Lock-Down Bit status active (not supported)

bits 2 to 15 Reserved for future use

(P+B)h

003Ch

78h

00h

(P+C)h

003Dh

7Ah

33h

(P+D)h

003Eh

7Ch

00h

(P+E)h

003Fh

7Eh

01h

OTP protection: No. of Protection Register fields

(P+F)h

0040h

80h

80h

Protection Register’s start address, least significant bits

(P+10)h

0041h

82h

00h

Protection Register’s start address, most significant bits

(P+11)h

0042h

84h

03h

(P+12)h

0043h

86h

03h

(P+13)h

0044h

88h

03h

(P+14)h

0045h

8Ah

00h

Synchronous mode configuration fields

(P+15)h

0046h

8Ch

Reserved for future use