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M68Z128W

OPERATIONAL MODE

The M68Z128W has a Chip Enable power down

feature which invokes an automatic standby mode

whenever either Chip Enable is de-asserted (E1 =

High or E2 = Low). An Output Enable (G) signal

provides a high speed tri-state control, allowing

fast read/write cycles to be achieved with the com-

mon I/O data bus. Operational modes are deter-

mined by device control inputs W, E1, and E2 as

summarized in the Operating Modes table.

Table 3. Operating Modes

Operation

E1

E2

W

G

DQ0-DQ7

Power

Read

Hi-Z

Active

Read

Data Output

Active

Write

X

Data Input

Active

Deselect

XX

X

Hi-Z

Standby

Deselect

X

X

X

Hi-Z

Standby

Table 4. AC Measurement Conditions

Note: Output Hi-Z is defined as the point where data is no longer

driven.

Input Rise and Fall Times

≤ 15ns

Input Pulse Voltages

0 to 3V

Input and Output Timing Ref. Voltages

1.5V

Figure 3. AC Testing Load Circuit

AI00697

3.3V

OUT

CL = 50pF or 5pF

CL includes JIG capacitance

1213

Ω

DEVICE

UNDER

TEST

1378

Ω

Note: 1. Sampled only, not 100% tested.

2. Outputs deselected.

Symbol

Parameter

Test

Condition

Min

Max

Unit

Input Capacitance on all pins (except DQ)

6pF

(2)

Output Capacitance

8pF