NAND interface

ST72681

10/32

4.2

NAND error correction

No NAND Flash memory arrays are guaranteed by manufacturers to be error-free. Error

occurrence depends on the Flash cell type (MLC or SLC).

The ST72681 embeds hardware and firmware mechanisms to correct the errors.

4.2.1

Hardware error correction

The ST72681 embeds a Reed-Solomon algorithm-based hardware cell. This cell directly

manages 512-byte data packets on the NAND I/O system.

Based on a data packet contents, the cell generates an 80-bit Error Correction Code (ECC)

consisting of 8 words each containing 10 bits.

During write operations to NAND memory, the 512-bytes of data and the ECC are stored

together in the same page. The ECC is stored in the corresponding Redundant Area (RA),

using 10 bytes.

During read operations, the 512-bytes of data and the 8 ECC words are read back and are

passed through the Reed-Solomon cell for decoding. The cell allows the correction of 4

symbols in this 520-symbol packet (512 symbols from data + 8 symbols from ECC).

The hardware cell gives 3 possible results:

in the Reed-Solomon cell and are ready to use.

4.2.2

Firmware error management

The firmware defines the error correction possibilities with the corrected data packet.

When data is not repairable, the block is considered as bad and replaced by another one.

See below for further information.

4.3

Management of bad NAND blocks

NAND device manufacturers deliver their products with factory-marked bad blocks. This

marking depends on the manufacturer and the NAND type (page size, memory technology,

etc.). The ST72681 supports all bad block markings currently available on the market.

4.3.1

Bad block identification

During firmware initialization, the MCU scans the entire NAND configuration to identify bad

blocks.

A bad block is defined as follows:

other page (page 127 for MLC NAND; page 1 for SLC NAND).