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ST72681/R21 数据表(PDF) 25 Page - STMicroelectronics

部件名 ST72681/R21
功能描述  USB 2.0 high-speed Flash drive controller
PDF  32 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST72681/R21 数据表(HTML) 25 Page - STMicroelectronics

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ST72681
Electrical characteristics
25/32
Figure 16.
Typical VDD33-VOH vs. VDD33 (I/O D8)
7.8
Control pin characteristics
7.8.1
Asynchronous RESET pin
TA = 0 to +55 °C unless otherwise specified.
Figure 17.
Typical RON on RESET pin
0
20
40
60
80
100
120
140
160
180
02
468
10
Ioh (mA)
Table 22.
RESET pin characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VIL
Input low level voltage (1)
1.
The level on the RESET pin must be free to go below the VIL max. level specified in Section 7.8.1:
Asynchronous RESET pin. Otherwise the reset will not be taken into account internally.
0.16 x
VDD33
V
VIH
Input high level voltage
0.85 x
VDD33
Vhys
Schmitt trigger voltage hysteresis1)
450
mV
RON
Pull-up equivalent resistor
VDD33 = 3.3V
20
40
80
k
Ω
VDD33 = 2V
100
teh(RSTL)
External reset pulse hold time (2)
2.
To guarantee the reset of the Device, a minimum pulse has to be applied to the RESET pin. All short
pulses applied on RESET pin with a duration below teh(RSTL) can be ignored. Not tested in production,
guaranteed by design.
2.5
µs
tg(RSTL)
Filtered glitch duration (3)
3.
The reset network protects the device against parasitic resets.
200
ns
tew(RSTL) External reset pulse duration
(4)
4.
The external reset duration must respect this timing to guarantee a correct start-up of the internal regulator
at power-up. Not tested in production, guaranteed by design.
500
µs
tiw(RSTL)
Internal reset pulse duration
2
tCPU
40
50
60
70
80
90
100
2
2.5
3
3.5
Vdd (V)



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