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Revision 1.04

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AS1113

Datasheet - D e t a i l e d D e s c r i p t i o n

Serial Interface

Data accesses are made serially via pins SDI and SDO. At each CLK rising edge, the signal present at pin SDI is

shifted into the first bit of the internal shift register and the other bits are shifted ahead of the first bit. The MSB is the

first bit to be clocked in. In error-detection mode the shift register will latch-in the corresponding error data of tempera-

ture-, open-, and short-error register with each falling edge of LD.

The 16-bit data register will latch the data of the shift register at each rising edge of LD. This data is then used to drive

the current generator output drivers to switch on the corresponding LEDs as OEN goes low.

Timing Diagrams

This section contains timing diagrams referenced in other sections of this data sheet.

Figure 8. Normal Mode Timing Diagram

Figure 9. Output Delay Timing Diagram

OEN

OUTNx

LD

SDO

SDI

CLK

tSU(L)

tH(L)

tW(L)

tW(CLK)

tP1

tH(D)

50%

50%

50%

50%

50%

50%

tSU(D)

OEN Low = Output Enabled

tP2

OUTNx High = Output Off

OUTNx Low = Output On

50%

50%

50%

tW(OE)

14XtSTAG

tP3

OEN

OUTN0

OUTN1

OUTN15

50%

50%

50%

50%

tOF

tOR

tSTAG

90%

90%

10%

10%

14XtSTAG

tSTAG

tP3

50%

50%

50%

50%