AS1130 datasheet(18/67 Pages) AMSOSRAM

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[v2-01] 2016-Oct-12

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AS1130 − Detailed Description

Figure 24:

Bus Protocol

The bus protocol (as shown in Figure 24) is defined as:

• Data transfer may be initiated only when the bus is not

busy.

• During data transfer, the data line must remain stable

whenever the clock line is HIGH. Changes in the data line

while the clock line is HIGH will be interpreted as control

signals.

The bus conditions are defined as:

• Bus Not Busy. Data and clock lines remain HIGH.

• Start Data Transfer. A change in the state of the data line,

from HIGH to LOW, while the clock is HIGH, defines a START

condition.

• Stop Data Transfer. A change in the state of the data line,

from LOW to HIGH, while the clock line is HIGH, defines

the STOP condition.

• Data Valid. The state of the data line represents valid data,

when, after a START condition, the data line is stable for

the duration of the HIGH period of the clock signal. There

is one clock pulse per bit of data. Each data transfer is

initiated with a START condition and terminated with a

STOP condition. The number of data bytes transferred

between START and STOP conditions is not limited and is

determined by the master device. The information is

transferred byte-wise and each receiver acknowledges

with a ninth-bit. Within the I²C bus specifications a

high-speed mode (3.4MHz clock rate) is defined.

SDI

SCLK

Slave Address

R/W

Direction Bit

START

23-7

ACK

MSB

Repeat if More Bytes Transferred

STOP or

Repeated

START

ACK from

Receiver

ACK from

Receiver

ACK

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