AS3715 datasheet(110/159 Pages) AMSOSRAM

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ams Datasheet

Page 109

[v1-03] 2015-Aug-10

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AS3715 − Register Description

Figure 119:

ReferenceControl

Note(s) and/or Footnote(s):

1. All frequencies, timings and delays in this datasheet are based on 4MHz clk_int.

Addr:35h

ReferenceControl

Bit

Bit Name

Default

Access

Bit Description

on_reset_delay

RW_SM

Sets the ONKEY/ENx long press delay time

0 : 8 sec

1 : 4 sec if onkey_lpress_reset=0; ONKEY/ENx long

press is disabled if onkey_lpress_reset=1

reg_low_bias_mode

RW_SM

clk_div2

RW_SM

Divide internal clock oscillator by 2 to reduce

quiescent current for low power operation

0 : Normal mode

1 : Internal clock frequency divided by two. All timings

are increased by two. Switching frequency of all DCDC

converters are divided by two. Reduced transient

performance of DCDC converters.

standby_mode_on

RW_SM

Setting to 1 sets the PMU into standby mode.

All regulators are disabled except those regulators

enabled by Reg_standby_mod.

XRESET will be pulled to low. A normal startup of all

regulators will be done with any interrupt

(has to be enabled before entering standby mode).

During this startup, regulators defined by Reg standby

mode register are continuously ON.

3:1

clk_int

b000

RW_SM

Sets the internal CLK frequency fCLK used for fuel

gauge, DCDCs, PWM, ...(1)

0 : 4 MHz (default)

1 : 3.8 MHz

2 : 3.6 MHz

3 : 3.4 MHz

4 : 3.2 MHz

5 : 3.0 MHz

6 : 2.8 MHz

7 : 2.6 MHz

low_power_on

RW_SM

Enable low power mode of internal reference.

0 : Standard mode

1 : Low power mode - all specification except noise

parameters are still valid. Iq reduced by approx. 30uA

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