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R5F10DMDCLFB 数据表(PDF) 77 Page - Renesas Technology Corp |
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R5F10DMDCLFB 数据表(HTML) 77 Page - Renesas Technology Corp |
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77 / 139 page  RL78/D1A 3. ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT) R01DS0463EJ0120 Rev. 1.20 Page 77 of 135 Mar 31, 2026 3.5.5 Serial interface: UART operation (128-pin only) TA = -40 to +85 °C 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD = ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V Item Symbol Conditions Min. Max. Unit Transfer rate T fMCK/6Note bps Theoretical value of the maximum transfer rate fCLK = 32 MHz, fMCK = fCLK 5.3 Mbps Note When CSI transfer is operated by DMA, it is necessary to concider DMA response time to decide cycle time. Caution Different voltage between EVDD and VDD is allowed only when LCDM register is initial value. Figure 3-9 UART connection diagram Figure 3-10. UART mode bit width (reference) Baud-rate tolerance 1/Transfer rate High-/low-level bit width TxD0 RxD0 VIH/VOH VIL/VOL RxD0 TxD TxD0 RxD User's device D1A |
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