R5F10DMDCLFB datasheet(23/139 Pages) RENESAS

23 / 139 page

RL78/D1A

1. OUTLINE

R01DS0463EJ0120 Rev. 1.20

Page 23 of 135

Mar 31, 2026

1.7 Outline of Functions

(1/4)

Item

48-pin

64-pin

80-pin

ROM

RAM

ROM/

RAM

capacities

512 KB

24 KB

384 KB

20 KB

256 KB

16 KB

√

128 KB

8 KB

√

96 KB

6 KB

√

64 KB

4 KB

√

48 KB

3 KB

√

32 KB

2 KB

√

24 KB

2 KB

√

Data flash memory

8 KB

Memory space

1 MB

General-purpose register

8 bits

× 32 registers (8 bits × 8 registers × 4 banks)

Main

System

clock

High-speed system

clock

1 to 20 MHz (VDD = 2.7 V to 5.5 V)

High-speed on-chip

oscillation clock

4/8/16/24/32 MHz (TA = -40 to 85

°C)

4/8/16/24 MHz (TA = -40 to 105

°C)

PLL

4 MHz

× 16/2 = 32 MHz, 8 MHz × 16/4 = 32 MHz (TA = -40 to 85 °C)

4 MHz

× 12/2 = 24 MHz, 8 MHz × 12/4 = 24 MHz (TA = -40 to 105 °C)

Subsystem clock

32.768 kHz

Low-speed on-chip oscillation clock

15 kHz

Minimum instruction execution time

0.03125

μs (Main system clock 32 MHz TA = -40 to +85 °C)

0.04167

μs (Main system clock 24 MHz TA = -40 to 105 °C)

30.5

μs (Subsystem clock 32.768 kHz operation)

Instruction set

• 8-bit operation,16-bit operation

• Multiplication (8 bits × 8 bits)

• Bit manipulation (Set, reset, test, and Boolean operation), etc.

I/O port

Total number of port

CMOS I/O port

N-ch open-drain

Selectable port

LED direct drive port

CMOS input port

CMOS output port

Timer

16-bit timer

8 ch

× 3 units

Real-time clock (RTC)

1 ch

Interval timer

1 ch

Watchdog timer (WDT)

1 ch

Timer output

RTC output

Clock output/buzzer output

10-bit resolution A/D converter

3+2

6+2

<R>

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