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R5F10DMDCLFB 数据表(PDF) 101 Page - Renesas Technology Corp

部件名 R5F10DMDCLFB
功能描述  RENESAS MCU
PDF  139 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

R5F10DMDCLFB 数据表(HTML) 101 Page - Renesas Technology Corp

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RL78/D1A
4. ELECTRICAL SPECIFICATIONS (L GRADE PRODUCT)
R01DS0463EJ0120 Rev. 1.20
Page 101 of 135
Mar 31, 2026
TA = -40 to +105
°C, 4.0 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V (2/2)
Parameter
Symbols
Conditions
Min.
Typ.
Max.
Unit
Input voltage, highNote 2
VIH1
Schmitt3 mode
0.8EVDD
EVDD
V
VIH2
Schmitt1 modeNote 3
0.65EVDD
EVDD
V
Input voltage, lowNote 2
VIL1
Schmitt3 mode
0
0.5EVDD
V
VIL2
Schmitt1 mode Note 3
0
0.35EVDD
V
Input hysteresis width
Note 2, 4
VIHYS1
Schmitt3 mode
0.1
0.19
0.29
V
VIHYS2
Schmitt1 mode Note 3
0.15
0.59
0.84
V
Output voltage, high Note
1
VOH1
IOH = -5.0 mA
EVDD-1.0
EVDD
V
IOH = -3.0 mA up to 6 pins
EVDD-0.5
EVDD
V
VOH2
IOH = -13.0 mA, P73 or P135 (SG port)
EVDD-0.7
EVDD
V
Output voltage, low
VOL1
IOL = 8.5 mA
0
0.7
V
IOL = 3.0 mA up to 6 pins
0
0.5
V
VOL2
IOL = 13.0 mA, P73 or P135 (SG port)
0
0.7
V
Input leakage current,
high
ILIH1
VI = EVDD
1
μA
Input leakage current,
low
ILIL1
VI = EVSS
-1
μA
On chip pull-up
resistance Note 5
RU
VI = EVSS
10
20
100
k
Ω
On chip pull-down
resistance Note 6
RD
VI = EVDD
100
k
Ω
Notes 1.
When P60 or P61 is set to Nch open drain mode, it does not drive high level output.
2.
Except P130 because it is output only port.
3.
P01, P10, P11, P17, P31, P40, P50 to P52, P55 to P57, P61, P63, P70, P110 to P117, P135 only.
4.
This value is defined by evaluation result.
5.
Except P130 and P137. Pull-up resistance is connected by software when pin is set to input mode.
6.
LCD segment shared pins only. Pull-down resistance is connected during reset.
Caution Different voltage between EVDD and VDD is allowed only when LCDM register is initial value.



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