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M48T02 数据表(PDF) 6 Page - STMicroelectronics |
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M48T02 数据表(HTML) 6 Page - STMicroelectronics |
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6 / 19 page ![]() M48T02, M48T12 6/19 Table 5. DC Characteristics Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. Outputs deselected. 3. Measured with Control Bits set as follows: R = '1'; W, ST, FT = '0.' 4. Negative spikes of –1V allowed for up to 10ns once per Cycle. OPERATION MODES As Figure 4, page 4 shows, the static memory ar- ray and the quartz controlled clock oscillator of the M48T02/12 are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE™ clock information in the bytes with addresses 7F8h-7FFh. The clock locations con- tain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 7F8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT™ READ/WRITE memory cells. The M48T02/12 includes a clock control cir- cuit which updates the clock bytes with current in- formation once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T02/12 also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condi- tion. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls be- low approximately 3V, the control circuitry con- nects the battery which maintains data and clock operation until valid power returns. Table 6. Operating Modes Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 10, page 11 for details. Symbol Parameter Test Condition(1) Min Max Unit ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA ILO (2) Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA ICC Supply Current Outputs open 80 mA ICC1 (3) Supply Current (Standby) TTL E = VIH 3mA ICC2 (3) Supply Current (Standby) CMOS E = VCC – 0.2V 3mA VIL (4) Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2.2 VCC + 0.3 V VOL Output Low Voltage IOL = 2.1mA 0.4 V VOH Output High Voltage IOH = –1mA 2.4 V Mode VCC E G W DQ0-DQ7 Power Deselect 4.75 to 5.5V or 4.5 to 5.5V VIH X X High Z Standby WRITE VIL X VIL DIN Active READ VIL VIL VIH DOUT Active READ VIL VIH VIH High Z Active Deselect VSO to VPFD(min) (1) X X X High Z CMOS Standby Deselect ≤ VSO(1) X X X High Z Battery Back-up Mode |
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