M48T02 datasheet(13/19 Pages) STMICROELECTRONICS

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M48T02, M48T12

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the

device is going to spend a significant amount of

time on the shelf, the oscillator can be turned off to

minimize current drain on the battery. The STOP

Bit is the MSB of the seconds register. Setting it to

a '1' stops the oscillator. The M48T02/12 is

shipped from STMicroelectronics with the STOP

Bit set to a '1.' When reset to a '0,' the M48T02/12

oscillator starts within one second.

Calibrating the Clock

The M48T02/12 is driven by a quartz-controlled

oscillator with a nominal frequency of 32,768 Hz.

A typical M48T02/12 is accurate within 1 minute

per month at 25°C without calibration. The devices

are tested not to exceed ± 35 PPM (parts per mil-

lion) oscillator frequency error at 25°C, which

equates to about ±1.53 minutes per month.

The oscillation rate of any crystal changes with

temperature. Figure 11, page 14 shows the fre-

quency error that can be expected at various tem-

peratures. Most clock chips compensate for

crystal frequency and temperature shift error with

cumbersome “trim” capacitors. The M48T02/12

design, however, employs periodic counter cor-

rection. The calibration circuit adds or subtracts

counts from the oscillator divider circuit at the di-

vide by 256 stage, as shown in Figure 12, page 14.

The number of times pulses are blanked (subtract-

ed, negative calibration) or split (added, positive

calibration) depends upon the value loaded into

the five-bit Calibration Byte found in the Control

tracting counts slows the clock down.

The Calibration Byte occupies the five lower order

bits in the Control register. This byte can be set to

represent any value between 0 and 31 in binary

form. The sixth bit is the Sign Bit; '1' indicates pos-

itive calibration, '0' indicates negative calibration.

Calibration occurs within a 64 minute cycle. The

first 62 minutes in the cycle may, once per minute,

have one second either shortened by 128 or

lengthened by 256 oscillator cycles. If a binary '1'

is loaded into the register, only the first 2 minutes

in the 64 minute cycle will be modified; if a binary

6 is loaded, the first 12 will be affected, and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 oscillator cycles for

every 125,829,120 actual oscillator cycles; that is

+4.068 or –2.034 PPM of adjustment per calibra-

tion step in the calibration register. Assuming that

the oscillator is in fact running at exactly 32,768Hz,

each of the 31 increments in the Calibration Byte

would represent +10.7 or –5.35 seconds per

month which corresponds to a total range of +5.5

or –2.75 minutes per month.

Two methods are available for ascertaining how

much calibration a given M48T02/12 may require.

The first involves simply setting the clock, letting it

run for a month and comparing it to a known accu-

rate reference (like WWV broadcasts). While that

may seem crude, it allows the designer to give the

end user the ability to calibrate his clock as his en-

vironment may require, even after the final product

is packaged in a non-user serviceable enclosure.

All the designer has to do is provide a simple utility

that accesses the Calibration Byte.

The second approach is better suited to a manu-

facturing environment, and involves the use of

some test equipment. When the Frequency Test

(FT) Bit, the seventh-most significant bit in the Day

at 32,768 Hz, the LSB (DQ0) of the Seconds Reg-

ister will toggle at 512 Hz. Any deviation from 512

Hz indicates the degree and direction of oscillator

frequency shift at the test temperature. For exam-

ple, a reading of 512.01024 Hz would indicate a

+20 PPM oscillator frequency error, requiring a –

10 (WR001010) to be loaded into the Calibration

Byte for correction.

Note: Setting or changing the Calibration Byte

does not affect the Frequency Test output fre-

quency. The device must be selected and ad-

dresses must be stable at Address 7F9 when

reading the 512 Hz on DQ0.

The FT Bit must be set using the same method

used to set the clock: using the WRITE Bit. The

LSB of the Seconds Register is monitored by hold-

ing the M48T02/12 in an extended READ of the

Seconds Register, but without having the READ

Bit set. The FT Bit MUST be reset to '0' for normal

clock operations to resume.

Note: It is not necessary to set the WRITE Bit

when setting or resetting the Frequency Test Bit

(FT) or the Stop Bit (ST).

For more information on calibration, see the Appli-

cation Note AN924, “TIMEKEEPER® Calibration.”

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