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RZ/N2L 数据表(PDF) 60 Page - Renesas Technology Corp

部件名 RZ/N2L
功能描述  RZ Arm-based High-end 32 & 64-bit MPUs
PDF  128 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

RZ/N2L 数据表(HTML) 60 Page - Renesas Technology Corp

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CKIO
tDACD
tDACD
Tr
A25 to A0
tAD1
tAD1
tCSD1
tRWD1
A12/A11*1
RD/WR#
tCSD1
DACK*2
Tc1
Trwl
D15 to D0
tBSD
BS#
tBSD
Row address
Column
address
tAD1
tAD1
tAD1
tAD1
WRITA
command
CS3#, CS2#
RAS#
tRASD1
tRASD1
tCASD1
CAS#
tCASD1
DQMLU, DQMLL
tDQMD1
tDQMD1
tWDH2
tWDD2
(High)
CKE
tRWD1
tRWD1
Trw
Trw
Note 1. Address pin to be connected to A10 of SDRAM.
Note 2. DACK is waveform when active-low is specified.
Figure 2.24
Synchronous DRAM single-write bus cycle (with auto precharge, WTRCD = 2 cycles, TRWL = 1
cycle)
RZ/N2L Datasheet
2. Electrical Characteristics
R01DS0397EJ0140 Rev.1.40
Mar 31, 2026
Page 60 of 128



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