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RZ/N2L 数据表(PDF) 64 Page - Renesas Technology Corp |
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RZ/N2L 数据表(HTML) 64 Page - Renesas Technology Corp |
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64 / 128 page ![]() CKIO tDACD tDACD Tc4 A25 to A0 tAD1 tCSD1 tRWD1 A12/A11*1 RD/WR# tCSD1 DACK*2 Tc1 Tc2 Tde tRWD1 D15 to D0 tBSD BS# tBSD Column address tAD1 tAD1 tAD1 READ command CS3#, CS2# RAS# tRASD1 tCASD1 CAS# tCASD1 DQMLU, DQMLL tDQMD1 tDQMD1 tRDH2 tRDS2 (High) CKE Tc3 Td4 Td1 Td2 Td3 tAD1 tAD1 tAD1 tRDH2 tRDS2 Note 1. Address pin to be connected to A10 of SDRAM. Note 2. DACK is waveform when active-low is specified. Figure 2.28 Synchronous DRAM burst-read bus cycle (read for 4 cycles) (bank active mode: READ command, same row address, CAS latency 2, WTRCD = 0 cycles) RZ/N2L Datasheet 2. Electrical Characteristics R01DS0397EJ0140 Rev.1.40 Mar 31, 2026 Page 64 of 128 |
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